IPR-PCIE/4 Altera, IPR-PCIE/4 Datasheet - Page 193
IPR-PCIE/4
Manufacturer Part Number
IPR-PCIE/4
Description
IP CORE Renewal Of IP-PCIE/4
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x4 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Testbench & Example Designs
Figure 5–5. Output from ebfm_disp_perf_sample Procedure
Altera Corporation
December 2006
# INFO:
ns
# INFO:
# INFO:
# INFO:
# INFO:
# INFO:
# INFO:
# INFO:
# INFO:
ebfm_disp_perf_sample Procedure
This procedure displays performance information to the standard output.
The procedure will also reset the performance counters on the next Root
Port BFM clock edge. Calling this routine effectively starts a new
performance sampling window. No performance count information is
lost from one sample window to the next.
An example of the output from this routine is shown in the following
figure:
The above example is from a VHDL version of the testbench. The Verilog
version may have slightly different formatting.
92850 ns PERF: Sample Duration: 5008
92850 ns PERF:
92850 ns PERF:
92850 ns PERF:
92850 ns PERF:
92850 ns PERF:
92850 ns PERF:
92850 ns PERF:
92850 ns PERF:
PCI Express Compiler Version 6.1
Tx MByte/sec: 1767
Rx MByte/sec: 1764
Tx Mbit/sec: 14134
Rx Mbit/sec: 14109
Tx Packets: 33
Rx Packets: 34
PCI Express Compiler User Guide
Tx Bytes: 8848
Rx Bytes: 8832
5–43
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