IPR-PCIE/4 Altera, IPR-PCIE/4 Datasheet - Page 179
IPR-PCIE/4
Manufacturer Part Number
IPR-PCIE/4
Description
IP CORE Renewal Of IP-PCIE/4
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x4 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
- Current page: 179 of 256
- Download datasheet (2Mb)
Testbench & Example Designs
Altera Corporation
December 2006
■
■
All of the files for the BFM are generated by the MegaWizard interface in
the testbench/<variation name> directory.
BFM Memory Map
The BFM shared memory is configured to be 2MB in size. The BFM shared
memory is mapped into the first 2MB of I/O space and also the first 2MB
of memory space. When the endpoint application generates an I/O or
memory transaction in this range, the BFM reads or writes the shared
memory.
Configuration Space Bus and Device Numbering
The root port interface is assigned to be device number 0 on internal bus
number 0.
The endpoint can be assigned to be any device number on any bus
number (greater than 0) through the call to procedure ebfm_cfg_rp_ep.
The specified bus number is assigned to be the secondary bus in the root
port configuration space.
modules and handles them at an RTL level to interface to the PCI
Express link. You do not need to access this module directly to adapt
the testbench to test your endpoint application.
VC0:3 Interfaces (altpcietb_bfm_vc_intf) — These interface
modules handle the VC-specific interfaces on the root port interface
model. They take requests from the BFM request interface and
generate the required PCI Express transactions. They handle
completions received from the PCI Express link and notify the BFM
request interface when requests are complete. Additionally, they
handle any requests received from the PCI Express link, and store or
fetch data from the shared memory before generating the required
completions.
Root port interface model (altpcietb_bfm_rpvar_64b_x8_pipen1b)
— This is an IP functional simulation model of a version of the
MegaCore function specially modified to support root port
operation. It’s application layer interface is very similar to the
application layer interface of the MegaCore function used for
endpoint mode.
PCI Express Compiler Version 6.1
PCI Express Compiler User Guide
5–29
Related parts for IPR-PCIE/4
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/1
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/8
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP NIOS II MEGACORE RENEW
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-XAUIPCS
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet: