IPR-PCIE/4 Altera, IPR-PCIE/4 Datasheet - Page 125
IPR-PCIE/4
Manufacturer Part Number
IPR-PCIE/4
Description
IP CORE Renewal Of IP-PCIE/4
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x4 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Specifications
Altera Corporation
December 2006
cfg_tcvcmap[23:0]
cfg_busdev[12:0]
cfg_prmcsr[31:0]
cfg_devcsr[31:0]
cfg_linkcsr[31:0]
Table 3–35. Configuration Space Signals
Signal
O
O
O
O
O
I/O
Configuration Space Signals
The signals in
configuration space registers that the application layer may need to
access.
Configuration traffic class/virtual channel mapping: The application layer uses this
signal to generate a transaction layer packet mapped to the appropriate virtual
channel based on the traffic class of the packet.
●
●
●
●
●
●
●
●
Configuration bus device: This signal generates a transaction ID for each transaction
layer packet, and indicates the bus and device number of the MegaCore function.
Because the MegaCore function only implements one function, the function number
of the transaction ID must be set to 000b.
●
●
Configuration primary control status register. The content of this register controls the
PCI status.
Configuration dev control status register. See PCI Express specification for details.
Configuration link control status register. See PCI Express specification for details.
cfg_tcvcmap[2:0]
cfg_tcvcmap[5:3]
cfg_tcvcmap[8:6]
cfg_tcvcmap[11:9]
cfg_tcvcmap[14:12]
cfg_tcvcmap[17:15]
cfg_tcvcmap[20:18]
cfg_tcvcmap[23:21]
cfg_busdev[12:5]
cfg_busdev[4:0]
PCI Express Compiler Version 6.1
Table 3–35
: Device number.
reflect the current values of several
: Mapping for TC0 (always 0).
: Mapping for TC1.
: Mapping for TC2.
: Bus number.
: Mapping for TC3.
: Mapping for TC4.
: Mapping for TC5.
: Mapping for TC6.
: Mapping for TC7.
Description
PCI Express Compiler User Guide
3–87
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