IPR-ED8B10B Altera, IPR-ED8B10B Datasheet - Page 8

• Manufacturer Part Number: IPR-ED8B10B
• Description: IP CORE Renewal Of IP-ED8B10B
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ED8B10B

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Encoder/Decoder, 8b/10b for Gigabit Ethernet and Fibre Channel
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
8
CASCADED DECODING
Two decoders can be cascaded to decode two words simultaneously. The
decoders are cascaded—in a similar fashion as the encoders—by
connecting the rdcascade output of the first decoder to the rdin input
of the second decoder, and by connecting the rdout output of the second
decoder to the rdin input of the first decoder. The rdforce inputs of
both decoders must be tied high.
To enable cascaded decoding, the data paths fed by the rdin and
rdforce inputs are not cascaded. If these inputs are to be used in non-
cascaded decoders, they should be delayed by one clock cycle with respect
to their corresponding datain and kin inputs.
Decoding Latency
The decoder is pipelined, thus it takes two clock cycles for a character to
be decoded. The decoded value—corresponding to the value of datain
sampled by the decoder on rising edge n—is output shortly after rising
edge n+1, and is available to be sampled on the rising edge of clock cycle
n+2. (See
Figure 6. Decoder Timing Diagram
clk
datain,
enable
dataout,
kout, kerr,
rdout, rderr
rdforce,
rdin
Figure 4 on page
a
n
b
a
7).
n+1
c
a
b
n+2
d
b
c
n+3
e
d
c
Altera Corporation
d
e
f
g
e
f