IPR-ED8B10B Altera, IPR-ED8B10B Datasheet - Page 6

• Manufacturer Part Number: IPR-ED8B10B
• Description: IP CORE Renewal Of IP-ED8B10B
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ED8B10B

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Encoder/Decoder, 8b/10b for Gigabit Ethernet and Fibre Channel
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
6
// The _pre2 registers are set at the same time as datain and kin.
reg rdforce_pre2;
reg rdin_pre2;
// The _pre1 registers provide an extra clock tick of delay
reg rdforce_pre1;
reg rdin_pre1;
always @ (posedge clk) begin
end
rdforce <= rdforce_pre1;
rdforce_pre1 <= rdforce_pre2;
rdin <= rdin_pre1;
rdin_pre1 <= rdin_pre2;
Encoding Latency
The encoder is pipelined, thus it takes three clock cycles for a character to
be encoded. The encoded value—corresponding to the values of datain
and kin sampled by the encoder on rising edge n—is output shortly after
rising edge n+2, and is available to be sampled on the rising edge of clock
cycle n+3. (See
To enable cascaded encoding, the data paths fed by the rdforce and
rdin inputs are not pipelined. Since rdforce and rdin are normally
only used in cascaded configurations, this should not be a problem.
In cases where the rdforce and rdin inputs are to be used in non-
cascaded configurations, they should be delayed two clock cycles with
respect to their corresponding datain and kin values. This can be
achieved by inserting two registers in series with each of the inputs to be
delayed, the following example Verilog code shows how to implement the
required delay registers.
Example: Adding delay to rdforce and rdin for non-cascaded
applications:
Figure 4 on page
7).
Altera Corporation