IPR-ED8B10B Altera, IPR-ED8B10B Datasheet - Page 5

• Manufacturer Part Number: IPR-ED8B10B
• Description: IP CORE Renewal Of IP-ED8B10B
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ED8B10B

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Encoder/Decoder, 8b/10b for Gigabit Ethernet and Fibre Channel
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 3. Cascaded Encoding
Note:
(1)
Altera Corporation
The enable, idle_ins, and rdforce signals are set high (logic 1).
datain
kin
[15:0]
[1:0]
Cascaded Encoding
Two encoders can be cascaded to allow for 16-bit word encoding. The
encoders are cascaded by connecting the rdcascade output of the most
significant byte (MSByte) encoder to the rdin input of the least significant
byte (LSByte) encoder, and by connecting the rdout output of the LSByte
encoder to the rdin input of the MSByte encoder. These connections
ensure proper running disparity computation. The rdforce inputs must
be asserted (active high) for the encoders to take into account the value on
the rdin inputs, rather than use their internally generated running
disparity. Both enable inputs must be high or low at the same time. The
kin [1] signal relates to datain[15:8], and kin[0] relates to
datain[7:0].
perform cascaded encoding.
clk
reset_n
kin [1]
enable
idle_ins
rdin
rdforce
clk
reset_n
kin [0]
enable
idle_ins
datain [7:0]
rdin
rdforce
datain [15:8]
Note (1)
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
Figure 3
shows two encoders connected together to
kerr
dataout [9:0]
valid
rdout
rdcascade
kerr
dataout [9:0]
valid
rdout
rdcascade
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