IP-XAUIPCS Altera, IP-XAUIPCS Datasheet - Page 8
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IP-XAUIPCS
Manufacturer Part Number
IP-XAUIPCS
Description
IP CORE - XAUI PHY
Manufacturer
Altera
Datasheet
1.IP-XAUIPCS.pdf
(120 pages)
Specifications of IP-XAUIPCS
Software Application
IP CORE, Interface And Protocols, ETHERNET
Supported Families
Stratix IV GT, Stratix V
Features
10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
Core Architecture
FPGA
Core Sub-architecture
Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Figure 1–1. Altera Modular PHY Design
Altera Transceiver PHY IP Core User Guide
To MAC
Embedded
Controller
To
Avalon-ST
Tx and Rx
Control & Status
Avalon-MM
Figure 1–1
PHY - Stratix V
illustrates the top level modules that comprise the PHY IP cores.
Hard logic for Stratix V, variable for Stratix IV
Soft logic for Stratix IV and Stratix V
Controller
Customized functionality
Reset
S
Avalon-MM PHY
Control & Status
PCI Express PIPE
Read & Write
Management
as required for:
Registers
Low Latency
10GBase-R
Interlaken
Custom
XAUI
PCS
M
PCS & PMA Control & Status
Register Memory Map
S
M
S
Rx Deserializer
PLL
Tx Serializer
Avalon-MM master interface
Avalon-MM slave interface
PMA
Offset Cancellation
S
Reconfiguration
Analog Settings
Transceiver
CDR
December 2010 Altera Corporation
Chapter 1: Introduction
To HSSI Pins
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