IP-XAUIPCS Altera, IP-XAUIPCS Datasheet - Page 74

• Manufacturer Part Number: IP-XAUIPCS
• Description: IP CORE - XAUI PHY
• Manufacturer: Altera

Specifications of IP-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–10
Table 6–8. PIPE Interface (Part 2 of 2)
Altera Transceiver PHY IP Core User Guide
pipe_txcompliance
pipe_txmargin
pipe_rate
pipe_powerdown<n>[1:0]
pipe_rxpolarity
pipe_rxelecidle
pipe_phystatus
pipe_rxstatus<n>[2:0]
rx_eidleinfersel[<n>-1:0]
pipe_txswing
Note to
(1) <n> is the number of lanes. The PHY (PIPE) supports ×1, ×4, ×8 operation.
Table
Signal Name
6–8:
(1)
(1)
Direction
Source
Source
Source
Source
Sink
Sink
Sink
Sink
Sink
Sink
When asserted for one cycle, sets the 8B/10B encoder output running
disparity to negative. Used when transmitting the compliance pattern. Refer
to section 6.11 of the
Architecture
Transmit V
sets the value for this signal based on the value from the Link Control 2
Register. This is 3 bits in the PIPE Specification.
Specifies the link frequency, as follows:
■
■
Figure 6–4 on page 6–11
to Gen2 and back to Gen1.
This signal requests the PHY to change its power state to the specified
state. The following encodings are defined:
■
■
■
■
When 1, instructs the PHY layer to invert the polarity on the 8B/10B
receiver decoding block.
When asserted, indicates receiver detection of an electrical idle.
This signal is used to communicate completion of several PHY requests.
This signal encodes receive status and error codes for the receive data
stream and receiver detection.The following encodings are defined:
■
■
■
■
■
■
■
■
When this option is set in the parameter editor, the RX interface infers
electrical idle instead of using analog circuitry to detect a device at the other
end of the link.
Indicates whether the transceiver is using full- or low-swing voltages as
defined by the tx_pipemargin.
■
■
0 –Gen1 operation, or 2.5 Gbps
1–Gen2 operation, or 5.0 Gbps
2b’00– P0, normal operation
2b’01–P0s, low recovery time latency, power saving state
2b’10–P1, longer recovery time (64 us maximum latency), lower power
state
2b’11–P2, lowest power state. (not supported)
000–receive data OK
001–1 SKP added
010–1 SKP removed
011–Receiver detected
100–Both 8B/10B decode error and (optionally) RX disparity error
101–Elastic buffer overflow
110–Elastic buffer underflow
111–Receive disparity error.
0–Full swing
1–Low swing
OD
margin selection. The PCI Express MegaCore function hard IP
for more information.
Intel PHY Interface for PCI Express (PIPE)
illustrates the timing of a rate switch from Gen1
Description
Chapter 6: PCI Express PHY (PIPE) IP Core
December 2010 Altera Corporation
Interfaces