IP-XAUIPCS Altera, IP-XAUIPCS Datasheet - Page 26

• Manufacturer Part Number: IP-XAUIPCS
• Description: IP CORE - XAUI PHY
• Manufacturer: Altera

Specifications of IP-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–8
Table 3–8. Mapping from XGMII RX Bus to the XGMII SDR Bus (Part 2 of 2)
Table 3–9. Avalon-MM PHY Management Interface
Altera Transceiver PHY IP Core User Guide
xgmii_rx_dc[17]
xgmii_rx_dc[25:18]
xgmii_rx_dc[26]
xgmii_rx_dc[34:27]
xgmii_rx_dc[35]
xgmii_rx_dc[43:36]
xgmii_rx_dc[44]
xgmii_rx_dc[52:45]
xgmii_rx_dc[53]
xgmii_rx_dc[61:54]
xgmii_rx_dc[62]
xgmii_rx_dc[70:63]
xgmii_rx_dc[71]
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_addr[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
Avalon-MM Interface
Signal Name
Signal Name
f
The Avalon-MM module provides access to the PCS and PMA registers, the
Transceiver Reconfiguration IP core, and the Low Latency PHY Controller IP core.
PHY management block includes Avalon-MM master and slave interfaces and acts as
a bridge. It transfers commands received on its Avalon-MM slave interface to its
Avalon-MM port.
Table 3–9
interface.
Refer to the “Typical Slave Read and Write Transfers” and “Master Transfers” sections in
the “Avalon Memory-Mapped Interfaces” chapter of the
timing diagrams.
describes the signals that comprise the Avalon-MM PHY Management
Direction
xgmii_sdr_ctrl[1]
xgmii_sdr_data[23:16]
xgmii_sdr_ctrl[2]
xgmii_sdr_data[31:24]
xgmii_sdr_ctrl[3]
xgmii_sdr_data[39:32]
xgmii_sdr_ctrl[4]
xgmii_sdr_data[47:40]
xgmii_sdr_ctrl[5]
xgmii_sdr_data[55:48]
xgmii_sdr_ctrl[6]
xgmii_sdr_data[63:56]
xgmii_sdr_ctrl[7]
Output
Output
Input
Input
Input
Input
Input
Input
XGMII Signal Name
The clock signal that controls the Avalon-MM PHY management,
calibration, and reconfiguration interfaces. For Stratix IV devices, the
maximum frequency is 50 MHz.
Global reset signal that resets the entire 10GBASE-R PHY. A positive
edge on this signal triggers the reset controller.
9-bit Avalon-MM address. Refer to for the address fields.
Input data.
Output data.
Write signal. Asserted high.
Read signal. Asserted high.
When asserted, indicates that the Avalon-MM slave interface is unable
to respond to a read or write request. When asserted, control signals
to the Avalon-MM slave interface must remain constant.
Description
Lane 1 control
Lane 2 data
Lane 2 control
Lane 3 data
Lane 3 control
Lane 4 data
Lane 4 control
Lane 5 data
Lane 5 control
Lane 6 data
Lane 6 control
Lane 7 data
Lane 7 control
Avalon Interface Specifications
Chapter 3: 10GBASE-R PHY IP Core
December 2010 Altera Corporation
Description
Interfaces
for