IP-XAUIPCS Altera, IP-XAUIPCS Datasheet - Page 70

• Manufacturer Part Number: IP-XAUIPCS
• Description: IP CORE - XAUI PHY
• Manufacturer: Altera

Specifications of IP-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–6
Table 6–6. Avalon-MM PHY Management Interface
Table 6–7. PCI Express PHY (PIPE) IP Core Registers (Part 1 of 4)
Altera Transceiver PHY IP Core User Guide
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
0x022
0x041
0x042
Word
Addr
PHY Management Signals
Signal Name
[31:0]
[31:0]
[1:0]
Bits
Table 6–6
interface.
Register Descriptions
Table 6–7
management interface using word addresses and a 32-bit embedded processor. A
single address space provides access to all registers.
R/W
RW
W
R
R
pma_tx_pll_is_locked
reset_ch_bitmask
reset_control (write)
reset_status(read)
describes the signals that comprise the Avalon-MM PHY Management
describes the registers that you can access over the Avalon-MM PHY
Direction
Register Name
Output
Output
PMA Common Control and Status Registers
Input
Input
Input
Input
Input
Input
Reset Control Registers
Avalon-MM clock input.
Global reset signal that resets the entire PHY (PIPE). A positive edge on
this signal triggers the reset controller. Refer to
for a timing diagram illustrating the reset sequence for a duplex channel.
9-bit Avalon-MM address.
Input data.
Output data.
Write signal.
Read signal.
When asserted, indicates that the Avalon-MM slave interface is unable to
respond to a read or write request. When asserted, control signals to the
Avalon-MM slave interface must remain constant.
Bit[P] indicates that the TX/CMU PLL (P) is locked to the
input reference clock. There is typically one
pma_tx_pll_is_locked bit per system.
Reset controller channel bitmask for digital resets. The
default value is all 1s. Channel <n> can be reset when
<n> = 1.
Writing a 1 to bit 0 initiates a TX digital reset using the reset
controller module. The reset affects channels enabled in the
reset_ch_bitmask. Writing a 1 to bit 1 initiates a RX
digital reset of channels enabled in the
reset_ch_bitmask.
Reading bit 0 returns the status of the reset controller TX
ready bit. Reading bit 1 returns the status of the reset
controller RX ready bit.
Description
Chapter 6: PCI Express PHY (PIPE) IP Core
Description
December 2010 Altera Corporation
Figure 1–4 on page 1–7
Interfaces