IP-XAUIPCS Altera, IP-XAUIPCS Datasheet - Page 110

• Manufacturer Part Number: IP-XAUIPCS
• Description: IP CORE - XAUI PHY
• Manufacturer: Altera

Specifications of IP-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

10–4
Table 10–2. Correspondences between XAUI PHY Stratix IV GX and Stratix V Device Signals (Part 3 of 3)
PCI Express PHY (PIPE)
Table 10–3. Comparison of ALTGX Megafunction and PCI Express PHY (PIPE) Parameters (Part 1 of 2)
Altera Transceiver PHY IP Core User Guide
reconfig_clk
reconfig_togxb
reconfig_fromgxb
Not available
Note to
(1) <n> = the number of lanes. <d> = the total deserialization factor from the pin to the FPGA fabric.
Number of channels
Channel width
Subprotocol
input clock frequency
Starting Channel Number
Enable low latency sync
Enable RLV with run length of
Enable electrical idle inference
functionality
ALTGX Parameter Name (Default Value)
Table
Parameter Differences
10–2:
Signal Name
Stratix IV GX Devices
—
This section lists the differences between the parameters and signals for the PCI
Express PHY (PIPE) IP core and the ALTGX megafunction when configured in the
PCI Express (PIPE) functional mode.
Table 10–3
ALTGX megafunction parameters.
lists the PCI Express PHY (PIPE) parameters and the corresponding
1
[3:0]
[16:0]
Avalon MM Management Interface
Transceiver Reconfiguration
Number of Lanes
Deserialization factor
Protocol Version
PLL reference clock frequency
pipe_low_latency_syncronous_mode
pipe_run_length_violation_checking Always on
Enable electrical idle inferencing
phy_mgmt_clk_in_mhz
Width
PCI Express PHY (PIPE) Parameter Name
phy_mgmt_clk_rst
phy_mgmt_clk
phy_mgmt_address
phy_mgmt_read
phy_mgmt_readdata
phy_mgmt_write
phy_mgmt_writedata
—
Not available
Not available
Not available
Signal Name
Chapter 10: Migrating from Stratix IV to Stratix V
Stratix V Devices
December 2010 Altera Corporation
Automatically set to 0.
Quartus II software handles
lane assignments.
For embedded reset
controller to calculate delays
Comments
PCI Express PHY (PIPE)
1
1
[8:0]
1
[31:0]
1
[31:0]
(Note 1)
Width
—
—
—