IP-XAUIPCS Altera, IP-XAUIPCS Datasheet - Page 22

• Manufacturer Part Number: IP-XAUIPCS
• Description: IP CORE - XAUI PHY
• Manufacturer: Altera

Specifications of IP-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–4
Performance and Resource Utilization
Table 3–3. 10GBASE-R PHY Performance and Resource Utilization—Stratix IV GT Device
Parameter Settings
Table 3–4. Parameters
Altera Transceiver PHY IP Core User Guide
1
4
10
Device family
Number of channels
Mode of operation
Reference Clock Frequency
Enable additional control and
status pins
Use external PMA control and
reconfig
Starting channel number
Channels
Name
f
Table 3–3
channel using the current version of the Quartus II software targeting a Stratix IV GT
device. The numbers of combinational ALUTs, logic registers, and memory bits are
rounded to the nearest 100.
To configure the 10GBASE-R PHY IP core in the parameter editor, click Installed
Plug-Ins > Interfaces >Ethernet> 10GBASE-R PHY v10.1. The 10GBASE-R PHY IP
core is available for the Stratix IV or Stratix V device family.
This section describes the 10GBASE-R PHY parameters, which you can set using the
parameter editor.
For a description of the Analog options, refer the to
page
8–4.
Stratix IV GT
Stratix V
1–32
Duplex
TX only
RX only
322.265625 MHz
644.53125 MHz
On/Off
On/Off
0–96
shows the typical expected device resource utilization for a single duplex
Combinational ALUTs
Value
15600
38100
5200
Table 3–4
Additional Options
General Options
The target family. Stratix V devices use a hard PCS. Stratix IV devices
use a soft PCS. Both devices use a hard PMA.
The total number of 10Gbase-R PHY channels.
Stratix V devices allow duplex, TX, or RX mode. Stratix IV GX devices
only support duplex mode.
Stratix V devices support both frequencies.Stratix IV GX devices only
support 644.53125 MHz.
If you turn this option on, the following 2 signals are brought out to
the top level of the IP core to facilitate debugging: hi_ber and
block_lock.
If you turn this option on, the PMA controller and reconfiguration
block are external, rather than included 10GBASE-R PHY IP core,
allowing you to use the same PMA controller and reconfiguration IP
cores for other protocols in the same transceiver quad. This option is
available in Stratix IV devices.
Specifies the starting channel number. Must be 0 or a multiple of 4.
You only need to set this parameter if you are using external PMA
and reconfiguration modules.
lists the settings available on General Options tab.
Logic Registers (Bits)
32100
4100
1300
Description
“PMA Analog Options” on
Performance and Resource Utilization
Chapter 3: 10GBASE-R PHY IP Core
December 2010 Altera Corporation
Memory Bits
18800
47500
4700