IP-XAUIPCS Altera, IP-XAUIPCS Datasheet - Page 79

• Manufacturer Part Number: IP-XAUIPCS
• Description: IP CORE - XAUI PHY
• Manufacturer: Altera

Specifications of IP-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Figure 7–1. Custom PHY IP Core
Device Family Support
December 2010 Altera Corporation
Custom
MAC
from
f
f
Avalon-ST Tx and Rx
Avalon-ST Reconfig
Avalon-MM Cntrl and Status
The Altera Custom PHY IP core is a generic PHY that you can customize for use in
Stratix V FPGAs. You can connect your application’s MAC-layer logic to the Custom
PHY to transmit and receive data at rates of 0.600–8.5 Gbps. You can parameterize the
physical coding sublayer (PCS) to include the functions that your application
requires. The following functions are available:
■
■
■
■
Your MAC layer must use the Avalon-ST to transmit and receive data from the
Custom PHY. The Avalon-ST protocol is a simple protocol designed for driving high
bandwidth, low latency, unidirectional data. To access control and status registers in
the Custom PHY, your design must include an embedded controller with an
Avalon-MM master interface. This is a standard, memory-mapped protocol that is
typically used to read and write registers and memory.
For more information about the Avalon-ST and Avalon-MM protocols, refer to the
Avalon Interface
Figure 7–1
For more detailed information about the Custom datapath and clocking, refer to the
“Custom Configurations with the Standard PCS” section in the
Configuration Datapath in Stratix V Devices
IP cores provide either final or preliminary support for target Altera device families.
These terms have the following definitions:
■
8B/10B encode and decode
Three different word alignment modes
Rate matching
Byte ordering
Final support—Verified with final timing models for this device.
illustrates the top-level signals and modules of the Custom PHY.
Specifications.
Stratix V FPGA
Custom PHY IP Core
Rate Match FIFO
Byte Ordering
Word Aligner
8B/10B
PCS:
chapter of the Stratix V Device Handbook.
Analog Buffers
SERDES
PMA:
7. Custom PHY IP Core
Altera Transceiver PHY IP Core User Guide
Custom Transceiver
Tx Serial Data
Rx Serial Data
Backplane
FPGA,
ASSP,
ASIC,
to
or