IP-XAUIPCS Altera, IP-XAUIPCS Datasheet - Page 77
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IP-XAUIPCS
Manufacturer Part Number
IP-XAUIPCS
Description
IP CORE - XAUI PHY
Manufacturer
Altera
Datasheet
1.IP-XAUIPCS.pdf
(120 pages)
Specifications of IP-XAUIPCS
Software Application
IP CORE, Interface And Protocols, ETHERNET
Supported Families
Stratix IV GT, Stratix V
Features
10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
Core Architecture
FPGA
Core Sub-architecture
Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Chapter 6: PCI Express PHY (PIPE) IP Core
6–13
Simulation
Example 6–1
shows the part of the Tcl script that you must edit.
Example 6–1. Simulation Variables
#################################################################################
##
## Set your language and top level design name here
##
#################################################################################
# language = verilog (verilog variant of the PHY IP) or vhdl (vhdl variant of the PHY IP)
# defaulted to verilog
set language verilog
#################################################################################
##
## Set your top level design name here
##
#################################################################################
# dut_name = top-level Verilog variant name as generated by Qmegawiz
set dut_name <top level Verilog design name>
# tb_name = top-level testbench name.
# Can be Verilog or VHDL depending on your Modelsim license.
set tb_name <top level Verilog/VHDL testbench name>
December 2010 Altera Corporation
Altera Transceiver PHY IP Core User Guide
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