PIC18F67J60T-I/PT Microchip Technology, PIC18F67J60T-I/PT Datasheet - Page 374
![128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67J60T-I/PT
Manufacturer Part Number
PIC18F67J60T-I/PT
Description
128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F66J65-IPT.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(480 pages)
3.PIC18F66J65-IPT.pdf
(4 pages)
4.PIC18F66J65-IPT.pdf
(10 pages)
Specifications of PIC18F67J60T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
39
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM183033 - BOARD DEMO INTERNET RADIOAC162064 - HEADER INTFC MPLABICD2 64/80/100AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67J60T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F97J60 FAMILY
BNOV
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39762E-page 374
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Overflow
If Overflow
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Overflow
BNOV
-128 ≤ n ≤ 127
if Overflow bit is ‘0’,
(PC) + 2 + 2n → PC
None
If the Overflow bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
‘n’
Q2
‘n’
=
=
=
=
=
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
n
0101
BNOV Jump
operation
Process
Process
Data
Data
No
Q3
Q3
nnnn
operation
operation
Write to
PC
No
No
Q4
Q4
nnnn
BNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Zero
If Zero
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Zero
BNZ
-128 ≤ n ≤ 127
if Zero bit is ‘0’,
(PC) + 2 + 2n → PC
None
If the Zero bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
‘n’
‘n’
Q2
Q2
=
=
=
=
=
© 2009 Microchip Technology Inc.
n
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
0001
BNZ
operation
Process
Process
Data
Data
No
Q3
Q3
Jump
nnnn
operation
operation
Write to
PC
No
No
Q4
Q4
nnnn
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