PIC18F67J60T-I/PT Microchip Technology, PIC18F67J60T-I/PT Datasheet - Page 244
![128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67J60T-I/PT
Manufacturer Part Number
PIC18F67J60T-I/PT
Description
128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F66J65-IPT.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(480 pages)
3.PIC18F66J65-IPT.pdf
(4 pages)
4.PIC18F66J65-IPT.pdf
(10 pages)
Specifications of PIC18F67J60T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
39
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM183033 - BOARD DEMO INTERNET RADIOAC162064 - HEADER INTFC MPLABICD2 64/80/100AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67J60T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F97J60 FAMILY
18.5.3.3
After the user application has processed a packet (or
part of the packet) and needs to free the occupied
buffer space used by the processed data, it must
advance the Receive Buffer Read Pointer pair,
ERXRDPT. The module always writes up to, but not
over, the memory pointed to by the ERXRDPT regis-
ters. If an attempt to overwrite the Receive Buffer Read
Pointer location occurs, the packet in progress is
aborted, the RXERIF flag is set and an interrupt is
generated (if enabled). In this manner, the hardware
will never overwrite unprocessed packets. Normally,
the ERXRDPT pair is advanced close to a value
pointed to by the Next Packet Pointer which precedes
the receive status vector for the current packet.
The
(ERXRDPTL register) is internally buffered to prevent
the pointer from moving when only one byte is updated.
To move the ERXRDPT pair, the application must write
to ERXRDPTL first. The write will update the internal
buffer but will not affect the register. When the applica-
tion writes to ERXRDPTH, the internally buffered low
byte will be loaded into the ERXRDPTL register at the
same time. The ERXRDPT bytes can be read in any
order. When they are read, the actual value of the
registers will be returned. As a result, the buffered low
byte is not readable.
In addition to advancing the Receive Buffer Read
Pointer, after each packet is fully processed, the appli-
cation must set the PKTDEC bit (ECON2<6>). This
causes the EPKTCNT register to decrement by 1. After
decrementing, if EPKTCNT is ‘0’, the PKTIF flag bit is
automatically cleared. Otherwise, it remains set, indi-
cating that additional packets are in the receive buffer
and are waiting to be processed. Attempting to decre-
ment EPKTCNT below 0 does not cause an underflow
to 255, but may cause an unintentional interrupt; the
application should avoid decrementing EPKTCNT in
this situation.
Additionally, if the EPKTCNT register ever maximizes
at 255, all new packets which are received will be
aborted, even if buffer space is available. To indicate
the error, the RXERIF is set and an interrupt is
generated (if enabled). To prevent this condition, the
user application must properly decrement the counter
whenever a packet is processed.
EQUATION 18-2:
DS39762E-page 244
If ERXWRPT > ERXRDPT, then
else
if ERXWRPT = ERXRDPT, then
else
Receive
Free Space = (ERXND – ERXST) – (ERXWRPT – ERXRDPT)
Free Space = (ERXND – ERXST)
Free Space = ERXRDPT – ERXWRPT – 1
Freeing Receive Buffer Space
Buffer
RECEIVE BUFFER FREE SPACE CALCULATION
Read
Pointer
Low
Byte
Because only one pointer is available to control buffer
area ownership, the application must process packets in
the order they are received. If a packet is to be saved
and processed later, the application should copy the
packet to an unused location in memory. This can be
done efficiently using the integrated DMA controller (see
Section 18.9 “Direct Memory Access Controller”).
18.5.3.4
At any time the application needs to know how much
receive buffer space is remaining, it should read the
Hardware Write Pointers (ERXWRPT registers) and
compare it with the ERXRDPT registers. Combined
with the known size of the receive buffer, the free space
can be derived.
When reading the ERXWRPT registers with the receive
hardware enabled, special care must be taken to ensure
the low and high bytes are read as a matching set.
To be assured that a matching set is obtained:
1.
2.
3.
4.
With the Hardware Write Pointers obtained, the free
space can be calculated as shown in Equation 18-2.
The hardware prohibits moving the Write Pointer to the
same value occupied by the ERXRDPT registers, so at
least one byte will always go unused in the buffer. The
Equation 18-2 calculation reflects the lost byte.
Note:
Read the EPKTCNT register and save its
contents.
Read ERXWRPTL and ERXWRPTH.
Read the EPKTCNT register again.
Compare the two packet counts. If they are not
the same, go back to step 2.
The ERXWRPT registers only update
when a packet has been successfully
received. If the application reads it just
before another packet is to be successfully
completed, the value returned could be
stale and off by the maximum frame length
permitted (MAMXFLH:MAMXFLL) plus 8.
Furthermore, as the application reads one
byte of the ERXWRPT registers, a new
packet may arrive and update the 13-bit
pointer before the application has an
opportunity to read the other byte of the
ERXWRPT registers.
Receive Buffer Free Space
© 2009 Microchip Technology Inc.
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