PIC18F67J60T-I/PT Microchip Technology, PIC18F67J60T-I/PT Datasheet - Page 227
![128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67J60T-I/PT
Manufacturer Part Number
PIC18F67J60T-I/PT
Description
128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F66J65-IPT.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(480 pages)
3.PIC18F66J65-IPT.pdf
(4 pages)
4.PIC18F66J65-IPT.pdf
(10 pages)
Specifications of PIC18F67J60T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
39
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM183033 - BOARD DEMO INTERNET RADIOAC162064 - HEADER INTFC MPLABICD2 64/80/100AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67J60T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC18F66J65-IPT PDF datasheet
- PIC18F66J65-IPT PDF datasheet #2
- PIC18F66J65-IPT PDF datasheet #3
- PIC18F66J65-IPT PDF datasheet #4
- Current page: 227 of 480
- Download datasheet (8Mb)
REGISTER 18-12: PHSTAT2: PHYSICAL LAYER STATUS REGISTER 2
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8-6
bit 5
bit 4-0
U-0
U-0
—
—
Unimplemented: Read as ‘0’
TXSTAT: PHY Transmit Status bit
1 = PHY is transmitting data
0 = PHY is not transmitting data
RXSTAT: PHY Receive Status bit
1 = PHY is receiving data
0 = PHY is not receiving data
COLSTAT: PHY Collision Status bit
1 = A collision is occuring (PHY is both transmitting and receiving while in Half-Duplex mode)
0 = A collision is not occuring
LSTAT: PHY Collision Status bit
1 = Link is up
0 = Link is down
Reserved: Ignore on read
Unimplemented: Read as ‘0’
Reserved: Ignore on read
Unimplemented: Read as ‘0’
U-0
U-0
—
—
W = Writable bit
‘1’ = Bit is set
TXSTAT
R-0
R-0
r
RXSTAT
R-0
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
COLSTAT
PIC18F97J60 FAMILY
R-0
U-0
—
LSTAT
R-0
U-0
—
x = Bit is unknown
R-x
U-0
—
r
DS39762E-page 227
U-0
U-0
—
—
bit 8
bit 0
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