PIC18F67J60T-I/PT Microchip Technology, PIC18F67J60T-I/PT Datasheet - Page 299
![128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67J60T-I/PT
Manufacturer Part Number
PIC18F67J60T-I/PT
Description
128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F66J65-IPT.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(480 pages)
3.PIC18F66J65-IPT.pdf
(4 pages)
4.PIC18F66J65-IPT.pdf
(10 pages)
Specifications of PIC18F67J60T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
39
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM183033 - BOARD DEMO INTERNET RADIOAC162064 - HEADER INTFC MPLABICD2 64/80/100AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67J60T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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19.4.17.1
During a Start condition, a bus collision occurs if:
a)
b)
During a Start condition, both the SDAx and the SCLx
pins are monitored.
If the SDAx pin is already low, or the SCLx pin is
already low, then all of the following occur:
• the Start condition is aborted;
• the BCLxIF flag is set; and
• the MSSP module is reset to its Idle state
The Start condition begins with the SDAx and SCLx
pins deasserted. When the SDAx pin is sampled high,
the
SSPxADD<6:0> and counts down to 0. If the SCLx pin
is sampled low while SDAx is high, a bus collision
occurs, because it is assumed that another master is
attempting to drive a data ‘1’ during the Start condition.
FIGURE 19-28:
© 2009 Microchip Technology Inc.
(Figure 19-28).
SSPxIF
BCLxIF
SDAx or SCLx are sampled low at the beginning
of the Start condition (Figure 19-28).
SCLx is sampled low before SDAx is asserted
low (Figure 19-29).
SDAx
SCLx
Baud
SEN
S
Bus Collision During a Start
Condition
Rate
condition if SDAx = 1, SCLx = 1
Generator
BUS COLLISION DURING START CONDITION (SDAx ONLY)
S bit and SSPxIF set because
Set SEN, enable Start
Start condition. Set BCLxIF.
SDAx sampled low before
SDAx goes low before the SEN bit is set.
Set BCLxIF,
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
is
SDAx = 0, SCLx = 1.
loaded
from
SSPxIF and BCLxIF are
cleared in software
PIC18F97J60 FAMILY
If the SDAx pin is sampled low during this count, the
BRG is reset and the SDAx line is asserted early
(Figure 19-30). If, however, a ‘1’ is sampled on the
SDAx pin, the SDAx pin is asserted low at the end of
the BRG count. The Baud Rate Generator is then
reloaded and counts down to 0. If the SCLx pin is
sampled as ‘0’ during this time, a bus collision does not
occur. At the end of the BRG count, the SCLx pin is
asserted low.
Note:
SEN cleared automatically because of bus collision.
MSSP module reset into Idle state.
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDAx before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SSPxIF and BCLxIF are
cleared in software
DS39762E-page 299
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