PIC18F67J60T-I/PT Microchip Technology, PIC18F67J60T-I/PT Datasheet - Page 239
![128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67J60T-I/PT
Manufacturer Part Number
PIC18F67J60T-I/PT
Description
128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F66J65-IPT.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(480 pages)
3.PIC18F66J65-IPT.pdf
(4 pages)
4.PIC18F66J65-IPT.pdf
(10 pages)
Specifications of PIC18F67J60T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
39
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM183033 - BOARD DEMO INTERNET RADIOAC162064 - HEADER INTFC MPLABICD2 64/80/100AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67J60T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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18.5.2
The Ethernet module’s MAC will automatically
generate the preamble and Start-of-Frame (SOF)
delimiter fields when transmitting. Additionally, the
MAC can generate any padding (if needed) and the
CRC if configured to do so. The application must
generate and write all other frame fields into the buffer
memory for transmission.
FIGURE 18-8:
© 2009 Microchip Technology Inc.
bit 7
bit 7-4
bit 3
bit 2
bit 1
bit 0
—
TRANSMITTING PACKETS
Unimplemented: Read as ‘0’
PHUGEEN: Per-Packet Huge Frame Enable bit
When POVERRIDE = 1:
1 = The packet will be transmitted in whole
0 = The MAC will transmit up to the number of bytes specified by the MAMXFL registers. If the packet
When POVERRIDE = 0:
This bit is ignored.
PPADN: Per-Packet Padding Enable bit
When POVERRIDE = 1:
1 = The packet will be zero-padded to 60 bytes if it is less than 60 bytes
0 = The packet will be transmitted without adding any padding bytes
When POVERRIDE = 0:
This bit is ignored.
PCRCEN: Per-Packet CRC Enable bit
When POVERRIDE = 1:
1 = A valid CRC will be calculated and attached to the frame
0 = No CRC will be appended. The last 4 bytes of the frame will be checked for validity as a CRC.
When POVERRIDE = 0:
This bit is ignored.
POVERRIDE: Per-Packet Override bit
1 = The values of PCRCEN, PPADN and PHUGEEN will override the configuration defined by
0 = The values in MACON3 will be used to determine how the packet will be transmitted
is larger than the bytes specified, it will be aborted after the MAMXFL registers specification is
reached.
MACON3
—
FORMAT FOR PER-PACKET CONTROL BYTES
—
—
PHUGEEN
PIC18F97J60 FAMILY
In addition, the Ethernet module requires a single
per-packet control byte to precede the packet for trans-
mission. The control byte is organized as shown in
Figure 18-8. Before transmitting packets, the MAC
registers, which alter the transmission characteristics,
should be initialized as documented in Section 18.4
“Module Initialization”.
PPADN
PCRCEN
DS39762E-page 239
POVERRIDE
bit 0
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