PIC18F67J60T-I/PT Microchip Technology, PIC18F67J60T-I/PT Datasheet - Page 249
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PIC18F67J60T-I/PT
Manufacturer Part Number
PIC18F67J60T-I/PT
Description
128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F66J65-IPT.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(480 pages)
3.PIC18F66J65-IPT.pdf
(4 pages)
4.PIC18F66J65-IPT.pdf
(10 pages)
Specifications of PIC18F67J60T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
39
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM183033 - BOARD DEMO INTERNET RADIOAC162064 - HEADER INTFC MPLABICD2 64/80/100AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67J60T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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18.8
To minimize microcontroller processing overhead, the
Ethernet module incorporates a range of different
receive filters which can automatically reject packets
which are not needed. Six different types of packet
filters are implemented:
• Unicast
• Multicast
• Broadcast
• Pattern Match
• Magic Packet™
• Hash Table
The individual filters are all configured by the ERXFCON
register (Register 18-20). More than one filter can be
active at any given time. Additionally, the filters can be
configured by the ANDOR bit to either logically AND or
logically OR the tests of several filters. In other words,
the filters may be set so that only packets accepted by
all active filters are accepted, or a packet accepted by
any one filter is accepted. The flowcharts in Figure 18-12
and Figure 18-13 show the effect that each of the filters
will have, depending on the setting of ANDOR.
The device can enter Promiscuous mode and receive
all legal packets by setting the ERXFCON register to
20h (enabling only the CRC filter for valid packets). The
proper setting of the register will depend on the
application requirements.
18.8.1
The Unicast receive filter checks the destination
address of all incoming packets. If the destination
address exactly matches the contents of the MAADR
registers, the packet meets the Unicast filter criteria.
18.8.2
The Multicast receive filter checks the destination
address of all incoming packets. If the Least Significant
bit of the first byte of the destination address is set, the
packet meets the Multicast filter criteria.
18.8.3
The Broadcast receive filter checks the destination
address of all incoming packets. If the destination
address is FF-FF-FF-FF-FF-FF, the packet meets the
Broadcast filter criteria.
© 2009 Microchip Technology Inc.
Receive Filters
UNICAST FILTER
MULTICAST FILTER
BROADCAST FILTER
PIC18F97J60 FAMILY
18.8.4
The Hash Table receive filter is typically used to receive
traffic sent to a specific Multicast group address.
Because it checks the specific destination address of
packets, it is capable of filtering out more unwanted
packets than the Multicast filter.
The filter performs a 32-bit CRC over the six destina-
tion address bytes in the packet, using the polynomial
4C11DB7h. From the resulting 32-bit binary number, a
6-bit value is derived from bits 28:23. This value in turn
points to location in a table formed by the Ethernet
Hash Table registers, ETH0 through ETH7. If the bit in
that location is set, the packet meets the Hash Table fil-
ter criteria and is accepted. The specific pointer values
for each bit location in the table are shown in
Table 18-9.
An example of the Hash Table operation is shown in
Example 18-1. In this case, the destination address
01-00-00-00-01-2C produces a Table Pointer value of
34h, which points to bit 4 of ETH6. If this bit is ‘1’, the
packet will be accepted.
By extension, clearing every bit in the Hash Table reg-
isters means that the filter criteria will never be met.
Similarly, if every bit in the Hash Table is set, the filter
criteria will always be met.
TABLE 18-9:
EXAMPLE 18-1:
EHT0
EHT1
EHT2
EHT3
EHT4
EHT5
EHT6
EHT7
Register
Packet Destination Address:
Result of CRC-32 with 4C11DB7h:
1101 1010 0000 1011 0100 0101 0111 0101
Pointer derived from bits 28:23 of CRC result:
Corresponding Hash Table Location:
HASH TABLE FILTER
07
0F
17
1F
27
2F
37
3F
7
0E
1E
2E
3E
BIT ASSIGNMENTS IN HASH
TABLE REGISTERS
06
16
26
36
6
Bit Number in Hash Table
DERIVING A HASH TABLE
LOCATION
0D
1D
2D
3D
05
15
25
35
5
110100 (binary), or 34 (hex)
01-00-00-00-01-2C (hex)
0C
1C
2C
3C
04
14
24
34
4
0B
1B
2B
3B
03
13
23
33
3
DS39762E-page 249
0A
1A
2A
3A
02
12
22
32
2
ETH6<4>
01
09
19
21
29
31
39
11
(binary)
1
00
08
10
18
20
28
30
38
0
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