PIC18F67J60T-I/PT Microchip Technology, PIC18F67J60T-I/PT Datasheet - Page 133
![128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67J60T-I/PT
Manufacturer Part Number
PIC18F67J60T-I/PT
Description
128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F66J65-IPT.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(480 pages)
3.PIC18F66J65-IPT.pdf
(4 pages)
4.PIC18F66J65-IPT.pdf
(10 pages)
Specifications of PIC18F67J60T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
39
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM183033 - BOARD DEMO INTERNET RADIOAC162064 - HEADER INTFC MPLABICD2 64/80/100AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67J60T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC18F66J65-IPT PDF datasheet
- PIC18F66J65-IPT PDF datasheet #2
- PIC18F66J65-IPT PDF datasheet #3
- PIC18F66J65-IPT PDF datasheet #4
- Current page: 133 of 480
- Download datasheet (8Mb)
REGISTER 9-9:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
SSP2IE
R/W-0
2:
(1)
Implemented in 100-pin devices only.
Implemented in 80-pin and 100-pin devices only.
SSP2IE: MSSP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)
1 = Enabled
0 = Disabled
RC2IE: EUSART2 Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
TX2IE: EUSART2 Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP5IE: CCP5 Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP4IE: CCP4 Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP3IE: ECCP3 Interrupt Enable bit
1 = Enabled
0 = Disabled
BCL2IE
R/W-0
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
(1)
W = Writable bit
‘1’ = Bit is set
RC2IE
R-0
(2)
TX2IE
R-0
(1)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F97J60 FAMILY
TMR4IE
R/W-0
(2)
(2)
(1)
CCP5IE
R/W-0
x = Bit is unknown
CCP4IE
R/W-0
DS39762E-page 133
CCP3IE
R/W-0
bit 0
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