PIC18F67J60T-I/PT Microchip Technology, PIC18F67J60T-I/PT Datasheet - Page 241
![128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67J60T-I/PT
Manufacturer Part Number
PIC18F67J60T-I/PT
Description
128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F66J65-IPT.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(480 pages)
3.PIC18F66J65-IPT.pdf
(4 pages)
4.PIC18F66J65-IPT.pdf
(10 pages)
Specifications of PIC18F67J60T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
39
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM183033 - BOARD DEMO INTERNET RADIOAC162064 - HEADER INTFC MPLABICD2 64/80/100AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67J60T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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TABLE 18-4:
© 2009 Microchip Technology Inc.
55-52
47-32
19-16
15-0
Bit
51
50
49
48
31
30
29
28
27
26
25
24
23
22
21
20
Zero
Transmit VLAN Tagged Frame
Backpressure Applied
Transmit Pause Control Frame
Transmit Control Frame
Total Bytes Transmitted on Wire
Transmit Underrun
Transmit Giant
Transmit Late Collision
Transmit Excessive Collision
Transmit Excessive Defer
Transmit Packet Defer
Transmit Broadcast
Transmit Multicast
Transmit Done
Transmit Length Out of Range
Transmit Length Check Error
Transmit CRC Error
Transmit Collision Count
Transmit Byte Count
TRANSMIT STATUS VECTORS
Field
0
Frame’s length/type field contained 8100h which is the VLAN protocol
identifier.
Reserved, do not use.
The frame transmitted was a control frame with a valid pause opcode.
The frame transmitted was a control frame.
Total bytes transmitted on the wire for the current packet, including all
bytes from collided attempts.
The transmission was aborted due to insufficient buffer memory
bandwidth to sustain the 10 Mbit/s transmit rate.
Byte count for frame was greater than the MAMXFL registers.
Collision occurred after 64 bytes had already been transmitted.
Packet was aborted after the number of collisions exceeded 15, the
retransmission maximum.
Packet was deferred in excess of 24,287 bit times (2.4287 ms), due to a
continuously-occupied medium.
Packet was deferred for at least one attempt but less than an excessive
defer.
Packet’s destination address was a Broadcast address.
Packet’s destination address was a Multicast address.
Transmission of the packet was completed successfully.
Indicates that frame type/length field was larger than 1500 bytes (type
field).
Indicates that frame length field value in the packet does not match the
actual data byte length and is not a type field. The FRMLNEN bit
(MACON3<1>) must be set to get this error.
The attached CRC in the packet did not match the internally generated
CRC.
Number of collisions the current packet incurred during transmission
attempts. It applies to successfully transmitted packets and as such, will
not show the possible maximum count of 16 collisions.
Total bytes in frame not counting collided bytes.
PIC18F97J60 FAMILY
Description
DS39762E-page 241
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