PIC16F689-E/ML Microchip Technology, PIC16F689-E/ML Datasheet - Page 57
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,20PIN,PLASTIC](/photos/6/64/66481/c04-126_ml_sml.jpg)
PIC16F689-E/ML
Manufacturer Part Number
PIC16F689-E/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,20PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F690DM-PCTLHS.pdf
(306 pages)
3.PIC16F677-IP.pdf
(2 pages)
4.PIC16F677-IP.pdf
(16 pages)
Specifications of PIC16F689-E/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
18
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PIN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F690DM-PCTLHS PDF datasheet #2
- PIC16F677-IP PDF datasheet #3
- PIC16F677-IP PDF datasheet #4
- Current page: 57 of 306
- Download datasheet (6Mb)
3.6
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bit of the OSCCON
register.
3.6.1
The System Clock Select (SCS) bit of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
• When the SCS bit of the OSCCON register = 0,
• When the SCS bit of the OSCCON register = 1,
3.6.2
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCCON register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<2:0> bits in the Configuration
Word register (CONFIG), or from the internal clock
source. In particular, OSTS indicates that the Oscillator
Start-up Timer (OST) has timed out for LP, XT or HS
modes.
3.7
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the INTOSC
as the clock source and go back to Sleep without
waiting for the primary oscillator to become stable.
© 2008 Microchip Technology Inc.
the system clock source is determined by
configuration of the FOSC<2:0> bits in the
Configuration Word register (CONFIG).
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<2:0>
bits of the OSCCON register. After a Reset, the
SCS bit of the OSCCON register is always
cleared.
Note:
Note:
Clock Switching
Two-Speed Clock Start-up Mode
SYSTEM CLOCK SELECT (SCS) BIT
Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-Safe
Clock Monitor, does not update the SCS bit
of the OSCCON register. The user can
monitor the OSTS bit of the OSCCON
register to determine the current system
clock source.
OSCILLATOR START-UP TIME-OUT
STATUS (OSTS) BIT
Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCCON register to
remain clear.
PIC16F631/677/685/687/689/690
When the Oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
enabled (see Section 3.4.1 “Oscillator Start-up Timer
(OST)”). The OST will suspend program execution until
1024 oscillations are counted. Two-Speed Start-up
mode minimizes the delay in code execution by
operating from the internal oscillator as the OST is
counting. When the OST count reaches 1024 and the
OSTS bit of the OSCCON register is set, program
execution switches to the external oscillator.
3.7.1
Two-Speed Start-up mode is configured by the
following settings:
• IESO (of the Configuration Word register) = 1;
• SCS (of the OSCCON register) = 0.
• FOSC<2:0> bits in the Configuration Word
Two-Speed Start-up mode is entered after:
• Power-on Reset (POR) and, if enabled, after
• Wake-up from Sleep.
If the external clock oscillator is configured to be
anything other than LP, XT or HS mode, then Two-
speed Start-up is disabled. This is because the external
clock oscillator does not require any stabilization time
after POR or an exit from Sleep.
3.7.2
1.
2.
3.
4.
5.
6.
7.
Internal/External Switchover bit (Two-Speed Start-
up mode enabled).
register (CONFIG) configured for LP, XT or HS
mode.
Power-up Timer (PWRT) has expired, or
Wake-up from Power-on Reset or Sleep.
Instructions begin execution by the internal
oscillator at the frequency set in the IRCF<2:0>
bits of the OSCCON register.
OST enabled to count 1024 clock cycles.
OST timed out, wait for falling edge of the
internal oscillator.
OSTS is set.
System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
System clock is switched to external clock
source.
TWO-SPEED START-UP MODE
CONFIGURATION
TWO-SPEED START-UP
SEQUENCE
DS41262E-page 55
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