PIC16F689-E/ML Microchip Technology, PIC16F689-E/ML Datasheet - Page 254
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,20PIN,PLASTIC](/photos/6/64/66481/c04-126_ml_sml.jpg)
PIC16F689-E/ML
Manufacturer Part Number
PIC16F689-E/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,20PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F690DM-PCTLHS.pdf
(306 pages)
3.PIC16F677-IP.pdf
(2 pages)
4.PIC16F677-IP.pdf
(16 pages)
Specifications of PIC16F689-E/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
18
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PIN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F690DM-PCTLHS PDF datasheet #2
- PIC16F677-IP PDF datasheet #3
- PIC16F677-IP PDF datasheet #4
- Current page: 254 of 306
- Download datasheet (6Mb)
PIC16F631/677/685/687/689/690
TABLE 17-12: SPI MODE REQUIREMENTS
FIGURE 17-16:
DS41262E-page 252
Param
No.
70*
71*
72*
73*
74*
75*
76*
77*
78*
79*
80*
81*
82*
83*
SCL
SDA
Note: Refer to Figure 17-3 for load conditions.
*
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
SS
SS
SC
SC
SC
SC
SS
SC
SC
SC
SC
SS
SC
SC
DI
DI
DO
DO
DO
DO
Symbol
These parameters are characterized but not tested.
only and are not tested.
V2
V2
L2
L2
H2
L2
H
L
H2
L2
R
F
H2
L2
H2
L2
R
F
V2
V2
SC
SC
SC
SC
DO
DI
DO
SS
DO
DI
DO
SS
SC
SC
L
L,
H,
L
H,
L
H
V
V
H,
Z
V,
H,
L
90
SS↓ to SCK↓ or SCK↑ input
SCK input high time (Slave mode)
SCK input low time (Slave mode)
Setup time of SDI data input to SCK edge
Hold time of SDI data input to SCK edge
SDO data output rise time
SDO data output fall time
SS↑ to SDO output high-impedance
SCK output rise time
(Master mode)
SCK output fall time (Master mode)
SDO data output valid after
SCK edge
SDO data output setup to SCK edge
SDO data output valid after SS↓ edge
SS ↑ after SCK edge
I
2
Condition
C™ BUS START/STOP BITS TIMING
Start
91
Characteristic
3.0-5.5V
2.0-5.5V
3.0-5.5V
2.0-5.5V
3.0-5.5V
2.0-5.5V
1.5T
T
T
CY
CY
Min.
100
100
T
Tcy
CY
10
—
—
—
—
—
—
—
—
—
CY
+ 20
+ 20
+ 40
Typ† Max. Units Conditions
10
25
10
10
25
10
—
—
—
—
—
—
—
—
—
—
—
92
© 2008 Microchip Technology Inc.
Condition
Stop
145
25
50
25
50
25
50
25
50
50
—
—
—
—
—
—
—
93
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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