PIC16F689-E/ML Microchip Technology, PIC16F689-E/ML Datasheet - Page 186

• Manufacturer Part Number: PIC16F689-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,20PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F689-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 18
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F631/677/685/687/689/690
13.5
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 13-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be
disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and Status bits
appropriately set). This could be useful in receiver
applications as a Line Activity Monitor mode.
FIGURE 13-3:
DS41262E-page 184
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
SDO
(CKE = 1)
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
Master Mode
SPI MODE WAVEFORM (MASTER MODE)
bit 7
bit 7
bit 7
bit 7
bit 6
bit 6
bit 5
bit 5
bit 4
bit 4
bit 3
bit 3
The clock polarity is selected by appropriately
programming the CKP bit of the SSPCON register. This
then, would give waveforms for SPI communication as
shown in Figure 13-3, Figure 13-5 and Figure 13-6,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
• F
• F
• F
• Timer2 output/2 (No SSP module, PIC16F690
Figure 13-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
only)
OSC
OSC
OSC
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
bit 2
bit 2
CY
)
bit 1
bit 1
CY
CY
)
)
© 2008 Microchip Technology Inc.
bit 0
bit 0
bit 0
bit 0
4 Clock
Modes