DSPIC30F5011-20E/PT Microchip Technology, DSPIC30F5011-20E/PT Datasheet - Page 146
DSPIC30F5011-20E/PT
Manufacturer Part Number
DSPIC30F5011-20E/PT
Description
IC,DSP,16-BIT,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F5011-20IPT.pdf
(220 pages)
4.DSPIC30F5011-20IPT.pdf
(16 pages)
5.DSPIC30F5011-20IPT.pdf
(6 pages)
6.DSPIC30F5011-20IPT.pdf
(14 pages)
7.DSPIC30F5011-20IPT.pdf
(26 pages)
Specifications of DSPIC30F5011-20E/PT
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F5011-20E/PTG
DSPIC30F501120EPT
DSPIC30F501120EPT
DSPIC30F501120EPT
DSPIC30F501120EPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5011-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20IP PDF datasheet #2
- DSPIC30F5011-20IPT PDF datasheet #3
- DSPIC30F5011-20IPT PDF datasheet #4
- DSPIC30F5011-20IPT PDF datasheet #5
- DSPIC30F5011-20IPT PDF datasheet #6
- DSPIC30F5011-20IPT PDF datasheet #7
- Current page: 146 of 220
- Download datasheet (4Mb)
dsPIC30F5011/5013
Table 20-5
register. Since the control bits within the RCON register
are R/W, the information in the table implies that all the
bits are negated prior to the action specified in the
condition column.
TABLE 20-5:
Table 20-6
conditions for the RCON register. In this case, it is not
assumed the user has set/cleared specific bits prior to
action specified in the condition column.
TABLE 20-6:
DS70116J-page 146
Power-on Reset
Brown-out Reset
MCLR Reset during normal
operation
Software Reset during
normal operation
MCLR Reset during Sleep
MCLR Reset during Idle
WDT Time-out Reset
WDT Wake-up
Interrupt Wake-up from Sleep PC + 2
Clock Failure Trap
Trap Reset
Illegal Operation Trap
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1:
Power-on Reset
Brown-out Reset
MCLR Reset during normal
operation
Software Reset during
normal operation
MCLR Reset during Sleep
MCLR Reset during Idle
WDT Time-out Reset
WDT Wake-up
Interrupt Wake-up from Sleep PC + 2
Clock Failure Trap
Trap Reset
Illegal Operation Reset
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1:
Condition
Condition
shows the Reset conditions for the RCON
When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
shows a second example of the bit
INITIALIZATION CONDITION FOR RCON REGISTER: CASE 1
INITIALIZATION CONDITION FOR RCON REGISTER: CASE 2
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000004
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000004
0x000000
0x000000
Program
Program
Counter
Counter
PC + 2
PC + 2
(1)
(1)
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
0
u
u
u
u
u
u
u
u
u
1
u
0
0
0
0
0
0
0
0
0
0
1
0
0
u
u
u
u
u
u
u
u
u
u
1
0
0
0
0
0
0
0
0
0
0
0
1
0
u
1
0
1
1
0
u
u
u
u
u
0
0
1
0
1
1
0
0
0
0
0
0
0
u
0
1
u
u
0
u
u
u
u
u
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
u
0
0
0
0
1
1
u
u
u
u
© 2011 Microchip Technology Inc.
0
0
0
0
0
1
0
0
0
0
0
0
0
u
0
0
0
1
0
u
u
u
u
u
0
0
0
0
1
0
0
1
1
0
0
0
0
u
0
0
1
0
0
1
1
u
u
u
1
0
0
0
0
0
0
0
0
0
0
0
1
0
u
u
u
u
u
u
u
u
u
u
1
1
u
u
u
u
u
u
u
u
u
u
1
1
0
0
0
0
0
0
0
0
0
0
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