DSPIC30F5011-20E/PT Microchip Technology, DSPIC30F5011-20E/PT Datasheet - Page 131

• Manufacturer Part Number: DSPIC30F5011-20E/PT
• Description: IC,DSP,16-BIT,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5011-20E/PT

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F5011-20E/PTG; DSPIC30F501120EPT; DSPIC30F501120EPT

Figure 19-2
conversion rates above 100 ksps. The dsPIC30F5013
is shown as an example.
FIGURE 19-2:
The configuration procedures below give the required
setup values for the conversion speeds above 100
ksps.
19.7.1
The following configuration items are required to
achieve a 200 ksps conversion rate.
• Comply with conditions provided in
• Connect external V
• Set SSRC<2.0> = 111 in the ADCON1 register to
• Enable automatic sampling by setting the ASAM
• Write the SMPI<3.0> control bits in the ADCON2
© 2011 Microchip Technology Inc.
the recommended circuit shown in
enable the auto convert option.
control bit in the ADCON1 register.
register for the desired number of conversions
between interrupts.
C2
0.1 μF
R2
10
V
DD
V
DD
200 KSPS CONFIGURATION
GUIDELINE
depicts the recommended circuit for the
C1
0.01 μF
REF
ADC VOLTAGE REFERENCE SCHEMATIC
1
2
3
4
5
6
7
8
9
10
V
V
13
14
15
16
17
18
19
20
+ and V
SS
DD
R1
10
REF
- pins following
Figure
Table
V
DD
19-2.
dsPIC30F5013
19-2.
V
DD
Note 1: Ensure adequate bypass capacitors are provided on each V
V
DD
• Configure the ADC clock period to be:
• Configure the sampling time to be 1 T
The following figure shows the timing diagram of the
ADC running at 200 ksps. The T
tion with the guidelines described above allows a con-
version speed of 200 ksps. See
example.
by writing to the ADCS<5:0> control bits in the
ADCON3 register.
writing: SAMC<4:0> = 00001.
dsPIC30F5011/5013
(14 + 1) x 200,000
V
V
60
59
58
57
56
55
54
53
52
50
49
DD
47
46
45
44
43
42
41
SS
1
V
See Note 1:
DD
C8
1 μF
C5
1 μF
V
AV
= 334 ns
DD
AD
DD
Example 19-1
C7
0.1 μF
C4
0.1 μF
selection in conjunc-
DS70116J-page 131
V
AV
DD
AD
DD
C6
0.01 μF
C3
0.01 μF
by
DD
for code
V
AV
DD
pin.
DD