LPC2292FBD144 NXP Semiconductors, LPC2292FBD144 Datasheet - Page 21

• Manufacturer Part Number: LPC2292FBD144
• Description: 16/32BIT ARM7 MCU, 256K FLASH, 144LQFP
• Manufacturer: NXP Semiconductors

Specifications of LPC2292FBD144

• No. Of I/o's: 112
• Ram Memory Size: 16KB
• Cpu Speed: 60MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 6
• Digital Ic Case: RoHS Compliant
• Core Size: 32bit
• Program Memory Size: 256KB
• Oscillator Type: External Only
• Controller Family/series: LPC22xx
• Rohs Compliant: Yes

NXP Semiconductors
LPC2292_2294_7
Product data sheet
6.12.1 Features
6.13.1 Features
6.13.2 Features available in LPC2292/LPC2294/01 only
6.13 SPI serial I/O controller
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The I
I
The LPC2292/LPC2294 each contain two SPIs. The SPI is a full duplex serial interface,
designed to be able to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
2
C-bus).
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Compliant with standard I
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex communication.
Combined SPI master and slave.
Maximum data bit rate of
Eight to 16 bits per frame.
When the SPI interface is used in Master mode, the SSELn pin is not needed (can be
used for a different function).
2
C-bus implemented in LPC2292/LPC2294 supports bit rate up to 400 kbit/s (Fast
2
C-bus may be used for test and diagnostic purposes.
Rev. 7 — 4 December 2008
16/32-bit ARM microcontrollers with external memory interface
1
2
C-bus interface.
8
of the input clock rate.
LPC2292/LPC2294
2
C-bus is a multi-master bus, it can be
© NXP B.V. 2008. All rights reserved.
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