DSPIC30F5011-30I/PTG Microchip Technology, DSPIC30F5011-30I/PTG Datasheet - Page 91

• Manufacturer Part Number: DSPIC30F5011-30I/PTG
• Description: 16BIT MCU-DSP 30MHZ, SMD, 30F5011
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-30I/PTG

• Core Frequency: 30MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Operating Temperature Range: -40°C To
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.0
The Inter-Integrated Circuit (I
complete hardware support for both Slave and Multi-
Master modes of the I
standard, with a 16-bit interface.
This module offers the following key features:
• I
• I
• I
• I
• Serial clock synchronization for I
• I
FIGURE 15-1:
15.1.2
I
SDA pin is data.
15.1.3
I2CCON and I2CSTAT are control and status registers,
respectively. The I2CCON register is readable and writ-
able. The lower 6 bits of I2CSTAT are read only. The
remaining bits of the I2CSTAT are read/write.
I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CRCV is the receive buffer as shown in Figure 15-1.
I2CTRN is the transmit register to which bytes are
written during a transmit operation, as shown in
Figure 15-2.
 2004 Microchip Technology Inc.
2
C has a 2-pin interface: the SCL pin is clock and the
operation.
master and slaves.
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
collision and will arbitrate accordingly.
2
2
2
2
2
C interface supporting both master and slave
C Slave mode supports 7 and 10-bit address.
C Master mode supports 7 and 10-bit address.
C port allows bidirectional transfers between
C supports multi-master operation; detects bus
I
2
C MODULE
PIN CONFIGURATION IN I
I
2
C REGISTERS
PROGRAMMER’S MODEL
Bit 15
Bit 15
2
C serial communication
2
C
TM
2
) module provides
C port can be
Bit 9
2
C MODE
Bit 8
Bit 7
Bit 7
Preliminary
15.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7 and 10-bit addressing.
Thus, the I
a master on an I
15.1.1
The following types of I
• I
• I
• I
See the I
The I2CADD register holds the slave address. A status
bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the baud rate generator reload value.
In receive operations, I2CRSR and I2CRCV together
form a double-buffered receiver. When I2CRSR
receives a complete byte, it is transferred to I2CRCV
and
transmission, the I2CTRN is not double-buffered.
Note:
2
2
2
dsPIC30F5011/5013
C slave operation with 7-bit address
C slave operation with 10-bit address
C master operation with 7 or 10-bit address
an
Operating Function Description
2
C programmer’s model in Figure 15-1.
2
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
interrupt
C module can operate either as a slave or
VARIOUS I
Following a RESTART condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
2
C bus.
I2CRCV (8 bits)
I2CTRN (8 bits)
I2CBRG (9 bits)
I2CCON (16 bits)
I2CSTAT (16 bits)
I2CADD (10 bits)
2
C Standard and Fast mode
pulse
2
C operation are supported:
2
C MODES
is
generated.
DS70116C-page 89
During