DSPIC30F5011-30I/PTG Microchip Technology, DSPIC30F5011-30I/PTG Datasheet - Page 212

• Manufacturer Part Number: DSPIC30F5011-30I/PTG
• Description: 16BIT MCU-DSP 30MHZ, SMD, 30F5011
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-30I/PTG

• Core Frequency: 30MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Operating Temperature Range: -40°C To
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F5011/5013
Data Address Space ........................................................... 25
Data Converter Interface (DCI) Module ............................ 117
Data EEPROM Memory ...................................................... 51
DC Characteristics ............................................................ 166
DCI Module
DS70116C-page 210
Write Back................................................................... 18
Alignment .................................................................... 28
Alignment (Figure) ...................................................... 28
Effect of Invalid Memory Accesses (Table)................. 28
MCU and DSP (MAC Class) Instructions Example..... 27
Memory Map ......................................................... 25, 26
Near Data Space ........................................................ 29
Software Stack ............................................................ 29
Spaces ........................................................................ 28
Width ........................................................................... 28
Erasing ........................................................................ 52
Erasing, Block ............................................................. 52
Erasing, Word ............................................................. 52
Protection Against Spurious Write .............................. 55
Reading....................................................................... 51
Write Verify ................................................................. 55
Writing ......................................................................... 53
Writing, Block .............................................................. 54
Writing, Word .............................................................. 53
BOR .......................................................................... 177
Brown-out Reset ....................................................... 176
I/O Pin Input Specifications ....................................... 174
I/O Pin Output Specifications .................................... 175
Idle Current (I
Low-Voltage Detect................................................... 175
LVDL ......................................................................... 176
Operating Current (I
Power-Down Current (I
Program and EEPROM............................................. 177
Temperature and Voltage Specifications .................. 166
Bit Clock Generator................................................... 121
Buffer Alignment with Data Frames .......................... 122
Buffer Control ............................................................ 117
Buffer Data Alignment ............................................... 117
Buffer Length Control ................................................ 122
COFS Pin .................................................................. 117
CSCK Pin .................................................................. 117
CSDI Pin ................................................................... 117
CSDO Mode Bit ........................................................ 123
CSDO Pin ................................................................. 117
Data Justification Control Bit ..................................... 121
Device Frequencies for Common Codec
Digital Loopback Mode ............................................. 123
Enable ....................................................................... 119
Frame Sync Generator ............................................. 119
Frame Sync Mode Control Bits ................................. 119
I/O Pins ..................................................................... 117
Interrupts ................................................................... 123
Introduction ............................................................... 117
Master Frame Sync Operation .................................. 119
Operation .................................................................. 119
Operation During CPU Idle Mode ............................. 124
Operation During CPU Sleep Mode .......................... 124
Receive Slot Enable Bits........................................... 122
Receive Status Bits ................................................... 123
Register Map............................................................. 125
Sample Clock Edge Control Bit................................. 121
Slave Frame Sync Operation .................................... 120
Slot Enable Bits Operation with Frame Sync ............ 122
CSCK Frequencies (Table)............................... 121
IDLE
) .................................................... 170
DD
)............................................. 167
PD
) ........................................ 172
Preliminary
Demonstration Boards
Development Support ....................................................... 159
Device Configuration
Device Configuration Registers
Device Overview................................................................... 5
Disabling the UART ............................................................ 99
Divide Support .................................................................... 14
DSP Engine ........................................................................ 15
Dual Output Compare Match Mode .................................... 82
E
Electrical Characteristics .................................................. 165
Enabling and Setting Up UART
Enabling the UART ............................................................. 99
Equations
Errata .................................................................................... 4
Evaluation and Programming Tools.................................. 163
Exception Sequence
External Clock Timing Characteristics
External Clock Timing Requirements ............................... 179
Slot Status Bits ......................................................... 123
Synchronous Data Transfers .................................... 122
Timing Characteristics
Timing Requirements
Transmit Slot Enable Bits ......................................... 121
Transmit Status Bits.................................................. 123
Transmit/Receive Shift Register ............................... 117
Underflow Mode Control Bit...................................... 123
Word Size Selection Bits .......................................... 119
PICDEM 1................................................................. 162
PICDEM 17............................................................... 162
PICDEM 18R ............................................................ 163
PICDEM 2 Plus......................................................... 162
PICDEM 3................................................................. 162
PICDEM 4................................................................. 162
PICDEM LIN ............................................................. 163
PICDEM USB ........................................................... 163
PICDEM.net Internet/Ethernet .................................. 162
Register Map ............................................................ 149
FBORPOR ................................................................ 147
FGS .......................................................................... 147
FOSC........................................................................ 147
FWDT ....................................................................... 147
Instructions (Table) ..................................................... 14
Multiplier ..................................................................... 17
Continuous Pulse Mode.............................................. 82
Single Pulse Mode...................................................... 82
AC............................................................................. 178
DC ............................................................................ 166
Alternate I/O ............................................................... 99
Setting Up Data, Parity and Stop Bit Selections ......... 99
A/D Conversion Clock............................................... 129
Baud Rate................................................................. 101
Bit Clock Frequency.................................................. 121
COFSG Period.......................................................... 119
Serial Clock Rate ........................................................ 94
Time Quantum for Clock Generation ........................ 111
Trap Sources .............................................................. 41
Type A, B and C Timer ............................................. 184
Type A Timer ............................................................ 184
Type B Timer ............................................................ 185
Type C Timer ............................................................ 185
AC-Link Mode................................................... 190
Multichannel, I
AC-Link Mode................................................... 190
Multichannel, I
2
2
S Modes................................... 188
S Modes................................... 189
 2004 Microchip Technology Inc.