LAN9218-MT SMSC, LAN9218-MT Datasheet - Page 80

• Manufacturer Part Number: LAN9218-MT
• Description: CONTROLLER, ENET, 10/100, 100TQFP
• Manufacturer: SMSC

Specifications of LAN9218-MT

• Data Rate: 100Mbps
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Supply Current: 40mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• Interface Type: HBI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.93 (11-27-07)
13-12
BITS
11-3
2
1
0
Threshold Control Bits (TR). These control the transmit threshold values
the MIL should use. These bits are used when the SF bit is reset. The host
can program the Transmit threshold by setting these bits. The intent is to
allow the MIL to transfer data to the final destination only after the threshold
value is met.
In 10Mbps mode (TTM = 1) the threshold is set as follows:
In 100Mbps mode (TTM = 0) the threshold is set by as follows:
Reserved
32/16-bit Mode. When set, the LAN9218 is set for 32-bit operation. When
clear, it is configured for 16-bit operation. This field is the value of the
D32/nD16 strap.
Soft Reset Time-out (SRST_TO). If a software reset is attempted when the
internal PHY is not in the operational state (RX_CLK and TX_CLK running),
the reset will not complete and the soft reset operation will time-out and this
bit will be set to a ‘1’. The host processor must correct the problem and
issue another soft reset.
Soft Reset (SRST). Writing 1 generates a software initiated reset. This reset
generates a full reset of the MAC CSR’s. The SCSR’s (system command
and status registers) are reset except for any NASR bits. Soft reset also
clears any TX or RX errors (TXE/RXE). This bit is self-clearing.
Notes:
Do not attempt a soft reset unless the internal PHY is fully awake and
operational. After a PHY reset, or when returning from a reduced power
state, the PHY must be given adequate time to return to the operational
state before a soft reset can be issued. The internal RX_CLK and TX_CLK
signals must be running for a proper software reset. Please refer to
Section 6.8, "Reset Timing," on page 125
The LAN9218 must always be read at least once after power-up, reset, or
upon return from a power-saving state or write operations will not function.
[13]
[13]
0
0
1
1
0
0
1
1
[12]
[12]
0
1
0
1
0
1
0
1
DESCRIPTION
DATASHEET
Threshold (DWORDS)
Threshold (DWORDS)
for details on PHY reset timing.
80
020h
040h
080h
100h
012h
018h
020h
028h
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
TYPE
R/W
RO
RO
RO
SC
SMSC
DEFAULT
Datasheet
LAN9218
00
0
0
-
-