LAN9218-MT SMSC, LAN9218-MT Datasheet - Page 30

• Manufacturer Part Number: LAN9218-MT
• Description: CONTROLLER, ENET, 10/100, 100TQFP
• Manufacturer: SMSC

Specifications of LAN9218-MT

• Data Rate: 100Mbps
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Supply Current: 40mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• Interface Type: HBI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.93 (11-27-07)
3.6.2
3.6.3
3.6.4
3.6.5
Default Mode - Word Swap Register equal to 0x00000000 or any value other than 0xFFFFFFFF
ADDRESS
A1 PIN
16-bit Bus Writes
The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit write). No ordering requirements exist. The processor can access either
the low or high word first, as long as the next write is performed to the other word. If a write to the
same word is performed, the LAN9218 disregards the transfer.
16-bit Bus Reads
The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit read). No ordering requirements exist. The processor can access either
the low or high word first, as long as the next read is performed from the other word. If a read to the
same word is performed, the data read is invalid and should be re-read. This is not a fatal error. The
LAN9218 will reset its read counters and restart a new cycle on the next read. The Upper 16 data pins
(D[31:16]) are not driven by the LAN9218 in 16-bit mode. These pins have internal pull-down’s and
the signals are left in a high-impedance state.
Big and Little Endian Support
The LAN9218 supports “Big-” or “Little-Endian” processors with either 16 or 32-bit busses. To support
big-endian processors, the hardware designer must explicitly invert the layout of the byte lanes.
Word Swap Function
Internally the LAN9218 is 32-bits wide. The LAN9218 supports a Word Swap Function when its Host
Bus Interface is configured to operate in 16-bit mode. This feature is controlled by the Word Swap
Register, which is described in
register affects how words on the data bus are written to or read from the Control and Status Registers
and the Transmit and Receive Data/Status FIFOs. Refer to
mode only)"
FIFO to the network, the low order word is always transmitted first, and when the LAN9218 receives
data from the network to the Receive Data FIFO, the low-order word is always received first.
This register only takes effect when the LAN9218 is configured to operate in 16-bit mode. In 32-bit
mode, this register is ignored and the upper data bits, D[31:16], are always mapped to the high-order
word, and the lower data bits, D[15:0] are always mapped to the low-order word.
A1 = 0
A1 = 1
below for more details. Whenever the LAN9218 transmits data from the Transmit Data
Table 3.7 Word Swap Control (16-bit mode only)
D[15:8]
Byte 1
Byte 3
BYTE ORDER
Section 5.3.17, "WORD_SWAP—Word Swap Control," on page
DATASHEET
Byte 0
Byte 2
D[7:0]
30
When A1=0, D[15:0] is mapped to the low order
words of CSRs and FIFOs. When A1=1, D[15:0] is
mapped to the high-order words of CSRs and
FIFOs. Since low-order words are always
transmitted/received first, A1=0 data will always
precede A1=1 data.
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Table 3.7, "Word Swap Control (16-bit
DESCRIPTION
SMSC
Datasheet
LAN9218
88. This