LAN9215-MT SMSC, LAN9215-MT Datasheet - Page 89

• Manufacturer Part Number: LAN9215-MT
• Description: CONTROLLER, ENET, NON-PCI, 100TQFP
• Manufacturer: SMSC

Specifications of LAN9215-MT

• Data Rate: 100Mbps
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Supply Current: 40mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• Interface Type: HBI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Highly Efficient 10/100 Ethernet Controller with HP Auto-MDIX
SMSC LAN9215
5.3.14
30:28
26:24
22:20
18:16
15:11
Bits
10:8
7:5
4:3
31
27
23
19
Reserved
LED[3:1] enable (LEDx_EN). A ‘1’ sets the associated pin as an LED output.
When cleared low, the pin functions as a GPIO signal.
Reserved
GPIO Interrupt Polarity 0-2 (GPIO_INT_POL). When set high, a high logic
level on the corresponding GPIO pin will set the corresponding INT_STS
register bit. When cleared low, a low logic level on the corresponding GPIO
pin will set the corresponding INT_STS register bit.
GPIO Interrupts must also be enabled in GPIOx_INT_EN in the INT_EN
register.
Note:
Reserved
EEPROM Enable (EEPR_EN). The value of this field determines the function
of the external EEDIO and EECLK:
Please refer to
Note:
Note:
Reserved
GPIO Buffer Type 0-2 (GPIOBUFn). When set, the output buffer for the
corresponding GPIO signal is configured as a push/pull driver. When cleared,
the corresponding GPIO set configured as an open-drain driver.
Reserved
GPIO Direction 0-2 (GPDIRn). When set, enables the corresponding GPIO
as output. When cleared the GPIO is enabled as an input.
Reserved
GPO Data 3-4 (GPODn). The value written is reflected on GPOn.
LED1/GPIO0 – bit 28
LED2/GPIO1 – bit 29
LED3/GPIO2 – bit 30
GPIO0 – bit 24
GPIO1 – bit 25
GPIO2 – bit 26
GPIO0 – bit 16
GPIO1 – bit 17
GPIO2 – bit 18
GPIO0 – bit 8
GPIO1 – bit 9
GPIO2 – bit 10
GPO3 – bit 3
GPO4 – bit 4
GPIO_CFG—General Purpose IO Configuration Register
This register configures the GPIO and LED functions.
Offset:
GPIO inputs must be active for greater than 40nS to be recognized
as interrupt inputs.
The host must not change the function of the EEDIO and EECLK
pins when an EEPROM read or write cycle is in progress. Do not
use reserved settings.
Regardless of whether the internal or external PHY is selected,
RX_DV, TX_CLK and RX_CLK reflect the signals on the internal
PHY and the MAC always drives TX_EN.
Table 5.4
for the EEPROM Enable bit function definitions.
Description
88h
DATASHEET
89
Size:
32 bits
Type
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
Revision 1.2 (03-29-06)
Default
0000
000
000
000
000
00
-
-
-
-
-
-