LAN9215-MT SMSC, LAN9215-MT Datasheet - Page 123
![CONTROLLER, ENET, NON-PCI, 100TQFP](/photos/19/0/190054/42334689_sml.jpg)
LAN9215-MT
Manufacturer Part Number
LAN9215-MT
Description
CONTROLLER, ENET, NON-PCI, 100TQFP
Manufacturer
SMSC
Specifications of LAN9215-MT
Data Rate
100Mbps
No. Of Ports
2
Ethernet Type
IEEE 802.3 / 802.3u
Supply Current
40mA
Supply Voltage Range
2.97V To 3.63V
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
TQFP
Interface Type
HBI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9215-MT
Manufacturer:
BROADCOM
Quantity:
450
Company:
Part Number:
LAN9215-MT
Manufacturer:
Standard
Quantity:
1 643
Company:
Part Number:
LAN9215-MT
Manufacturer:
SMSC
Quantity:
9
Part Number:
LAN9215-MT
Manufacturer:
SMSC
Quantity:
20 000
Highly Efficient 10/100 Ethernet Controller with HP Auto-MDIX
SMSC LAN9215
6.3
SYMBOL
nCS, nRD
t
t
t
t
t
t
t
t
csdv
acyc
t
csh
asu
adv
don
doff
doh
A[7:5]
A[4:1]
Data Bus
ah
In this mode, performance is improved by allowing up to 16, WORD read cycles back-to-back. PIO
Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these
control signals must go high between bursts for the period specified.
Note: The “Data Bus” width is 16 bits
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
PIO Burst Reads
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address Setup to nCS, nRD valid
Address Stable to Data Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
Figure 6.2 PIO Burst Read Cycle Timing
Table 6.4 PIO Burst Read Timing
DATASHEET
123
MIN
165
13
0
0
0
0
TYP
Revision 1.2 (03-29-06)
MAX
30
40
7
UNITS
ns
ns
ns
ns
ns
ns
ns