LAN9215-MT SMSC, LAN9215-MT Datasheet
![CONTROLLER, ENET, NON-PCI, 100TQFP](/photos/19/0/190054/42334689_sml.jpg)
LAN9215-MT
Manufacturer Part Number
LAN9215-MT
Description
CONTROLLER, ENET, NON-PCI, 100TQFP
Manufacturer
SMSC
Specifications of LAN9215-MT
Data Rate
100Mbps
No. Of Ports
2
Ethernet Type
IEEE 802.3 / 802.3u
Supply Current
40mA
Supply Voltage Range
2.97V To 3.63V
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
TQFP
Interface Type
HBI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9215-MT
Manufacturer:
BROADCOM
Quantity:
450
Company:
Part Number:
LAN9215-MT
Manufacturer:
Standard
Quantity:
1 643
Company:
Part Number:
LAN9215-MT
Manufacturer:
SMSC
Quantity:
9
Part Number:
LAN9215-MT
Manufacturer:
SMSC
Quantity:
20 000
PRODUCT FEATURES
Highlights
Target Applications
Key Benefits
SMSC LAN9215
1.A minor PCB change is required. An Application Note showing how to
migrate an existing
Optimized for medium performance applications
Efficient architecture with low CPU overhead
Easily interfaces to most 16-bit embedded CPU’s
Integrated PHY with HP Auto-MDIX
Supports audio & video streaming over Ethernet:
Compatible with existing LAN9118 family members
Basic cable, satellite, and IP set-top boxes
Digital video recorders
Video-over IP Solutions, IP PBX & video phones
Wireless routers & access points
Audio distribution systems
Printers, kiosks, security systems
General embedded applications
Non-PCI Ethernet controller for medium-performance
Eliminates dropped packets
Minimizes CPU overhead
Reduces system cost and increases design flexibility
SRAM-like interface easily interfaces to most
multiple standard-definition (SD) MPEG2 streams
applications
— 16-bit interface
— Burst-mode read support
— External MII Interface
— Internal buffer memory can store over 200 packets
— Automatic PAUSE and back-pressure flow control
— Supports Slave-DMA
— Interrupt Pin with Programmable Hold-off timer
embedded CPU’s or SoC’s
LAN9115
design to the
LAN9215
will be provided.
DATASHEET
1
* Third party brands and names are the property of their respective owners.
Reduced Power Modes
Single chip Ethernet controller
Flexible address filtering modes
Integrated 10/100 Ethernet PHY
High-Performance host bus interface
Miscellaneous features
3.3V Power Supply with 5V tolerant I/O
0 to 70°C
— Numerous power management modes
— Wake on LAN*
— Magic packet wakeup*
— Wakeup indicator event signal
— Link Status Change
— Fully compliant with IEEE 802.3/802.3u standards
— Integrated Ethernet MAC and PHY
— 10BASE-T and 100BASE-TX support
— Full- and Half-duplex support
— Full-duplex flow control
— Backpressure for half-duplex flow control
— Preamble generation and removal
— Automatic 32-bit CRC generation and checking
— Automatic payload padding and pad removal
— Loop-back modes
— One 48-bit perfect address
— 64 hash-filtered multicast addresses
— Pass all multicast
— Promiscuous mode
— Inverse filtering
— Pass all incoming with status report
— Disable reception of broadcast packets
— Supports HP Auto-MDIX
— Auto-negotiation
— Supports energy-detect power down
— Simple, SRAM-like interface
— 16-bit data bus
— 16Kbyte FIFO with flexible TX/RX allocation
— One configurable host interrupt
— Low-profile, lead-fee 100-pin TQFP package
— Integrated 1.8V regulator
— General Purpose Timer
— Optional EEPROM interface
— Support for 3 status LEDs multiplexed with
LAN9215
Highly Efficient 10/100
Ethernet Controller
with HP Auto-MDIX
Programmable GPIO signals
Revision 1.2 (03-29-06)
Datasheet