LAN9215-MT SMSC, LAN9215-MT Datasheet - Page 51
![CONTROLLER, ENET, NON-PCI, 100TQFP](/photos/19/0/190054/42334689_sml.jpg)
LAN9215-MT
Manufacturer Part Number
LAN9215-MT
Description
CONTROLLER, ENET, NON-PCI, 100TQFP
Manufacturer
SMSC
Specifications of LAN9215-MT
Data Rate
100Mbps
No. Of Ports
2
Ethernet Type
IEEE 802.3 / 802.3u
Supply Current
40mA
Supply Voltage Range
2.97V To 3.63V
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
TQFP
Interface Type
HBI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Company
Part Number
Manufacturer
Quantity
Price
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LAN9215-MT
Manufacturer:
BROADCOM
Quantity:
450
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LAN9215-MT
Manufacturer:
Standard
Quantity:
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Company:
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Manufacturer:
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Highly Efficient 10/100 Ethernet Controller with HP Auto-MDIX
SMSC LAN9215
3.14.5
3.14.6
3.14.6.1
BITS
6:3
7
2
1
0
Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility.
Collision Count. This counter indicates the number of collisions that occurred before the packet was
transmitted. It is not valid when excessive collisions (bit 8) is also set.
Excessive Deferral. If the deferred bit is set in the control register, the setting of the excessive
deferral bit indicates that the transmission has ended because of a deferral of over 24288 bit times
during transmission.
Underrun Error. When set, this bit indicates that the transmitter aborted the associated frame
because of an underrun condition of the TX data FIFO. TX Underrun will cause the assertion of the
TXE error flag.
Deferred. When set, this bit indicates that the current packet transmission was deferred.
Calculating Actual TX Data FIFO Usage
The following rules are used to calculate the actual TX data FIFO space consumed by a TX Packet:
Transmit Examples
TX Example 1
In this example a single, 111-Byte Ethernet packet will be transmitted. This packet is divided into three
buffers. The three buffers are as follows:
Buffer 0:
Buffer 1:
Buffer 2:
Figure 3.14, "TX Example 1" illustrates the TX command structure for this example, and also shows
how data is passed to the TX data FIFO.
TX command 'A' is stored in the TX data FIFO for every TX buffer
TX command 'B' is written into the TX data FIFO when the First Segment (FS) bit is set in TX
command 'A'
Any DWORD-long data added as part of the “Data Start Offset” is removed from each buffer before
the data is written to the TX data FIFO. Any data that is less than 1 DWORD is passed to the TX
data FIFO.
Payload from each buffer within a Packet is written into the TX data FIFO.
Any DWORD-long data added as part of the End Padding is removed from each buffer before the
data is written to the TX data FIFO. Any end padding that is less than 1 DWORD is passed to the
TX data FIFO
7-Byte “Data Start Offset”
79-Bytes of payload data
16-Byte “Buffer End Alignment”
0-Byte “Data Start Offset”
15-Bytes of payload data
16-Byte “Buffer End Alignment”
10-Byte “Data Start Offset”
17-Bytes of payload data
16-Byte “Buffer End Alignment”
DATASHEET
DESCRIPTION
51
Revision 1.2 (03-29-06)