DP83848VYB National Semiconductor, DP83848VYB Datasheet - Page 8

• Manufacturer Part Number: DP83848VYB
• Description: TRANSCEIVER, ENET PHY, 10/100, 48LQFP
• Manufacturer: National Semiconductor

Specifications of DP83848VYB

• Data Rate: 100Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u
• Supply Current: 92mA
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: LQFP
• No.: RoHS Compliant
• Interface Type: MII Serial, RMII
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

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Signal Name
RX_ER
RXD_0
RXD_1
RXD_2
RXD_3
CRS/
CRS_DV
COL
X1
X2
25MHz_OUT
Signal Name
1.3 CLOCK INTERFACE
S, O, PU
S, O, PD
S, O, PU
S, O, PU
Type
Type
O
O
I
Pin #
41
43
44
45
46
40
42
Pin #
34
33
25
MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid
symbol has been detected within a received packet in 100 Mb/s mode.
RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever an invalid symbol is
detected, and CRS_DV is asserted in 100 Mb/s mode.
This pin is not required to be used by a MAC in either MII or RMII mode, since the Phy is required
to corrupt data on a receive error.
This pin is not used in SNI mode.
MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK,
25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data
when RX_DV is asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1
clock, 50 MHz.
SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchronously to the RX_CLK.
RXD_0 contains valid data when CRS is asserted. RXD[3:1] are not used in this mode.
MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle.
RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and
Receive Data Valid indications. For a detailed description of this signal, see the RMII
Specification.
SNI CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. It is used to
frame valid receive data on the RXD_0 signal.
MII COLLISION DETECT: Asserted high to indicate detection of a collision condition
(simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a
duration of approximately 1µs at the end of transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is
no heartbeat function during 10 Mb/s full duplex operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC
will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine
collision.
SNI COLLISION DETECT: Asserted high to indicate detection of a collision condition
(simultaneous transmit and receive activity) in 10 Mb/s SNI mode.
CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the
DP83848VYB and must be connected to a 25 MHz 0.005% (±50 ppm) clock source. The
DP83848VYB supports either an external crystal resonator connected across pins X1 and
X2, or an external CMOS-level oscillator source connected to pin X1 only.
RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode
and must be connected to a 50 MHz 0.005% (±50 ppm) CMOS-level oscillator source.
CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external
25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS
oscillator clock source is used.
25 MHz CLOCK OUTPUT:
In MII mode, this pin provides a 25 MHz clock output to the system.
In RMII mode, this pin provides a 50 MHz clock output to the system.
This allows other devices to use the reference clock from the DP83848VYB without requiring
additional clock sources.
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Description
Description