DP83848VYB National Semiconductor, DP83848VYB Datasheet - Page 17

• Manufacturer Part Number: DP83848VYB
• Description: TRANSCEIVER, ENET PHY, 10/100, 48LQFP
• Manufacturer: National Semiconductor

Specifications of DP83848VYB

• Data Rate: 100Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u
• Supply Current: 92mA
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: LQFP
• No.: RoHS Compliant
• Interface Type: MII Serial, RMII
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

3.0 Functional Description
The DP83848VYB supports several modes of operation using
the MII interface pins. The options are defined in the following
sections and include:
— MII Mode
— RMII Mode
— 10 Mb Serial Network Interface (SNI)
The modes of operation can be selected by strap options or
register control. For RMII mode, it is required to use the strap
option, since it requires a 50 MHz clock instead of the normal
25 MHz.
In each of these modes, the IEEE 802.3 serial management
interface is operational for device configuration and status.
The serial management interface of the MII allows for the
configuration and control of multiple PHY devices, gathering
of status, error information, and the determination of the type
and capabilities of the attached PHY(s).
3.1 MII INTERFACE
The DP83848VYB incorporates the Media Independent In-
terface (MII) as specified in Clause 22 of the IEEE 802.3u
standard. This interface may be used to connect PHY devices
to a MAC in 10/100 Mb/s systems. This section describes the
nibble wide MII data interface.
The nibble wide MII data interface consists of a receive bus
and a transmit bus each with control signals to facilitate data
transfer between the PHY and the upper layer (MAC).
3.1.1 Nibble-wide MII Data Interface
Clause 22 of the IEEE 802.3u specification defines the Media
Independent Interface. This interface includes a dedicated
receive bus and a dedicated transmit bus. These two data
buses, along with various control and status signals, allow for
the
DP83848VYB and the upper layer agent (MAC).
The receive interface consists of a nibble wide data bus RXD
[3:0], a receive error signal RX_ER, a receive data valid flag
RX_DV, and a receive clock RX_CLK for synchronous trans-
fer of the data. The receive clock operates at either 2.5 MHz
to support 10 Mb/s operation modes or at 25 MHz to support
100 Mb/s operational modes.
The transmit interface consists of a nibble wide data bus TXD
[3:0], a transmit enable control signal TX_EN, and a transmit
clock TX_CLK which runs at either 2.5 MHz or 25 MHz.
Additionally, the MII includes the carrier sense signal CRS, as
well as a collision detect signal COL. The CRS signal asserts
to indicate the reception of data from the network or as a
function of transmit data in Half Duplex mode. The COL signal
asserts as an indication of a collision which can occur during
half-duplex operation when both a transmit and receive op-
eration occur simultaneously.
3.1.2 Collision Detect
For Half Duplex, a 10BASE-T or 100BASE-TX collision is de-
tected when the receive and transmit channels are active
simultaneously. Collisions are reported by the COL signal on
the MII.
If the DP83848VYB is transmitting in 10 Mb/s mode when a
collision is detected, the collision is not reported until seven
bits have been received while in the collision state. This pre-
vents a collision being reported incorrectly due to noise on the
network. The COL signal remains set for the duration of the
collision.
simultaneous
exchange
of
data
between
the
17
If a collision occurs during a receive operation, it is immedi-
ately reported by the COL signal.
When heartbeat is enabled (only applicable to 10 Mb/s oper-
ation), approximately 1µs after the transmission of each pack-
et, a Signal Quality Error (SQE) signal of approximately 10 bit
times is generated (internally) to indicate successful trans-
mission. SQE is reported as a pulse on the COL signal of the
MII.
3.1.3 Carrier Sense
Carrier Sense (CRS) is asserted due to receive activity, once
valid data is detected via the squelch function during
10 Mb/s operation. During 100 Mb/s operation CRS is assert-
ed when a valid link (SD) and two non-contiguous zeros are
detected on the line.
For 10 or 100 Mb/s Half Duplex operation, CRS is asserted
during either packet transmission or reception.
For 10 or 100 Mb/s Full Duplex operation, CRS is asserted
only due to receive activity.
CRS is deasserted following an end of packet.
3.2 REDUCED MII INTERFACE
The DP83848VYB incorporates the Reduced Media Inde-
pendent Interface (RMII) as specified in the RMII specification
(rev1.2) from the RMII Consortium. This interface may be
used to connect PHY devices to a MAC in 10/100 Mb/s sys-
tems using a reduced number of pins. In this mode, data is
transferred 2-bits at a time using the 50 MHz RMII_REF clock
for both transmit and receive. The following pins are used in
RMII mode:
— TX_EN
— TXD[1:0]
— RX_ER (optional for MAC)
— CRS_DV
— RXD[1:0]
— X1 (RMII Reference clock is 50 MHz)
In addition, the RMII mode supplies an RX_DV signal which
allows for a simpler method of recovering receive data without
having to separate RX_DV from the CRS_DV indication. This
is especially useful for diagnostic testing where it may be de-
sirable to externally loop Receive MII data directly to the
transmitter.
Since the reference clock operates at 10 times the data rate
for 10 Mb/s operation, transmit data is sampled every 10
clocks. Likewise, receive data will be generated every 10th
clock so that an attached device can sample the data every
10 clocks.
RMII mode requires a 50 MHz oscillator be connected to the
device X1 pin. A 50 MHz crystal is not supported.
To tolerate potential frequency differences between the 50
MHz reference clock and the recovered receive clock, the re-
ceive RMII function includes a programmable elasticity buffer.
The elasticity buffer is programmable to minimize propagation
delay based on expected packet size and clock accuracy.
This allows for supporting a range of packet sizes including
jumbo frames.
The elasticity buffer will force Frame Check Sequence errors
for packets which overrun or underrun the FIFO. Underrun
and Overrun conditions can be reported in the RMII and By-
pass Register (RBR). The following table indicates how to
program the elasticity buffer fifo (in 4-bit increments) based
on expected max packet size and clock accuracy. It assumes
both clocks (RMII Reference clock and far-end Transmitter
clock) have the same accuracy.
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