DP83848VYB National Semiconductor, DP83848VYB Datasheet - Page 14

• Manufacturer Part Number: DP83848VYB
• Description: TRANSCEIVER, ENET PHY, 10/100, 48LQFP
• Manufacturer: National Semiconductor

Specifications of DP83848VYB

• Data Rate: 100Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u
• Supply Current: 92mA
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: LQFP
• No.: RoHS Compliant
• Interface Type: MII Serial, RMII
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

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If the DP83848VYB completes Auto-Negotiation as a result
of Parallel Detection, bits 5 and 7 within the ANLPAR register
will be set to reflect the mode of operation present in the Link
Partner. Note that bits 4:0 of the ANLPAR will also be set to
00001 based on a successful parallel detection to indicate a
valid 802.3 selector field. Software may determine that nego-
tiation completed via Parallel Detection by reading a zero in
the Link Partner Auto-Negotiation Able bit once the Auto-Ne-
gotiation Complete bit is set. If configured for parallel detect
mode and any condition other than a single good link occurs
then the parallel detect fault bit will be set.
2.1.4 Auto-Negotiation Restart
Once Auto-Negotiation has completed, it may be restarted at
any time by setting bit 9 (Restart Auto-Negotiation) of the BM-
CR to one. If the mode configured by a successful Auto-
Negotiation loses a valid link, then the Auto-Negotiation
process will resume and attempt to determine the configura-
tion for the link. This function ensures that a valid configura-
tion is maintained if the cable becomes disconnected.
A renegotiation request from any entity, such as a manage-
ment agent, will cause the DP83848VYB to halt any transmit
data and link pulse activity until the break_link_timer expires
(~1500 ms). Consequently, the Link Partner will go into link
fail and normal Auto-Negotiation resumes. The DP83848VYB
will resume Auto-Negotiation after the break_link_timer has
expired by issuing FLP (Fast Link Pulse) bursts.
2.1.5 Enabling Auto-Negotiation via Software
It is important to note that if the DP83848VYB has been ini-
tialized upon power-up as a non-auto-negotiating device
(forced technology), and it is then required that Auto-Negoti-
ation or re-Auto-Negotiation be initiated via software, bit 12
(Auto-Negotiation Enable) of the Basic Mode Control Register
(BMCR) must first be cleared and then set for any Auto-Ne-
gotiation function to take effect.
2.1.6 Auto-Negotiation Complete Time
Parallel detection and Auto-Negotiation take approximately
2-3 seconds to complete. In addition, Auto-Negotiation with
next page should take approximately 2-3 seconds to com-
plete, depending on the number of next pages sent.
Refer to Clause 28 of the IEEE 802.3u standard for a full de-
scription of the individual timers related to Auto-Negotiation.
2.2 AUTO-MDIX
When enabled, this function utilizes Auto-Negotiation to de-
termine the proper configuration for transmission and recep-
tion of data and subsequently selects the appropriate MDI pair
for MDI/MDIX operation. The function uses a random seed to
control switching of the crossover circuitry. This implementa-
tion complies with the corresponding IEEE 802.3 Auto-Nego-
tiation and Crossover Specifications.
Auto-MDIX is enabled by default and can be configured via
strap or via PHYCR (19h) register, bits [15:14].
Neither Auto-Negotiation nor Auto-MDIX is required to be en-
abled in forcing crossover of the MDI pairs. Forced crossover
can be achieved through the FORCE_MDIX bit, bit 14 of
PHYCR (19h) register.
Note: Auto-MDIX will not work in a forced mode of operation.
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2.3 PHY ADDRESS
The 5 PHY address inputs pins are shared with the RXD[3:0]
pins and COL pin are shown below.
The DP83848VYB can be set to respond to any of 32 possible
PHY addresses via strap pins. The information is latched into
the PHYCR register (address 19h, bits [4:0]) at device power-
up and hardware reset. The PHY Address pins are shared
with the RXD and COL pins. Each DP83848VYB or port shar-
ing an MDIO bus in a system must have a unique physical
address.
The DP83848VYB supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). Strapping PHY Address 0
puts the part into Isolate Mode. It should also be noted that
selecting PHY Address 0 via an MDIO write to PHYCR will
not put the device in Isolate Mode. See Section 2.3.1 MII Iso-
late Mode for more information.
For further detail relating to the latch-in timing requirements
of the PHY Address pins, as well as the other hardware con-
figuration pins, refer to the Reset summary in Section 6.0
Reset Operation.
Since the PHYAD[0] pin has weak internal pull-up resistor and
PHYAD[4:1] pins have weak internal pull-down resistors, the
default setting for the PHY address is 00001 (0x01h).
Refer to Figure 1 for an example of a PHYAD connection to
external components. In this example, the PHYAD strapping
results in address 000101 (0x03h).
2.3.1 MII Isolate Mode
The DP83848VYB can be put into MII Isolate mode by writing
to bit 10 of the BMCR register or by strapping in Physical Ad-
dress 0. It should be noted that selecting Physical Address 0
via an MDIO write to PHYCR will not put the device in the MII
isolate mode.
When in the MII isolate mode, the DP83848VYB does not re-
spond to packet data present at TXD[3:0], TX_EN inputs and
presents a high impedance on the TX_CLK, RX_CLK,
RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When in
Isolate mode, the DP83848VYB will continue to respond to all
management transactions.
While in Isolate mode, the PMD output pair will not transmit
packet data but will continue to source 100BASE-TX scram-
bled idles or 10BASE-T normal link pulses.
The DP83848VYB can Auto-Negotiate or parallel detect to a
specific technology depending on the receive signal at the
PMD input pair. A valid link can be established for the receiver
even when the DP83848VYB is in Isolate mode.
Pin #
42
43
44
45
46
TABLE 2. PHY Address Mapping
PHYAD Function
PHYAD0
PHYAD1
PHYAD2
PHYAD3
PHYAD4
RXD Function
RXD_0
RXD_1
RXD_2
RXD_3
COL