DP83848VYB National Semiconductor, DP83848VYB Datasheet - Page 43

• Manufacturer Part Number: DP83848VYB
• Description: TRANSCEIVER, ENET PHY, 10/100, 48LQFP
• Manufacturer: National Semiconductor

Specifications of DP83848VYB

• Data Rate: 100Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u
• Supply Current: 92mA
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: LQFP
• No.: RoHS Compliant
• Interface Type: MII Serial, RMII
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Not Compliant

Bit
15
14
13
12
11
10
9
8
7
6
7.2 EXTENDED REGISTERS
7.2.1 PHY Status Register (PHYSTS)
This register provides a single location within the register set for quick access to commonly accessed information.
DESCRAMBLER LOCK
POLARITY STATUS
RECEIVE ERROR
PAGE RECEIVED
FALSE CARRIER
SIGNAL DETECT
REMOTE FAULT
MII INTERRUPT
SENSE LATCH
MDIX MODE
RESERVED
Bit Name
LATCH
TABLE 21. PHY Status Register (PHYSTS), address 10h
0, RO/LH
0, RO/LH
0, RO/LL
0, RO/LL
Default
0, RO
0, RO
0, RO
0, RO
0, RO
0, RO
RESERVED: Write ignored, read as 0.
MDIX mode as reported by the Auto-Negotiation logic:
This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX
bits in the PHYCR register. When MDIX is enabled, but not forced, this bit will
update dynamically as the Auto-MDIX algorithm swaps between MDI and
MDIX configurations.
1 = MDI pairs swapped
(Receive on TPTD pair, Transmit on TPRD pair)
0 = MDI pairs normal
(Receive on TRD pair, Transmit on TPTD pair)
Receive Error Latch:
This bit will be cleared upon a read of the RECR register.
1 = Receive error event has occurred since last read of RXERCNT (address
15h, Page 0).
0 = No receive error event has occurred.
Polarity Status:
This bit is a duplication of bit 4 in the 10BTSCR register. This bit will be cleared
upon a read of the 10BTSCR register, but not upon a read of the PHYSTS
register.
1 = Inverted Polarity detected.
0 = Correct Polarity detected.
False Carrier Sense Latch:
This bit will be cleared upon a read of the FCSR register.
1 = False Carrier event has occurred since last read of FCSCR (address 14h).
0 = No False Carrier event has occurred.
100Base-TX qualified Signal Detect from PMA:
This is the SD that goes into the link monitor. It is the AND of raw SD and
descrambler lock, when address 16h, bit 8 (page 0) is set. When this bit is
cleared, it will be equivalent to the raw SD from the PMD.
100Base-TX Descrambler Lock from PMD.
Link Code Word Page Received:
This is a duplicate of the Page Received bit in the ANER register, but this bit
will not be cleared upon a read of the PHYSTS register.
1 = A new Link Code Word Page has been received. Cleared on read of the
ANER (address 06h, bit 1).
0 = Link Code Word Page has not been received.
MII Interrupt Pending:
1 = Indicates that an internal interrupt is pending. Interrupt source can be
determined by reading the MISR Register (12h). Reading the MISR will clear
the Interrupt.
0 = No interrupt pending.
Remote Fault:
1 = Remote Fault condition detected (cleared on read of BMSR (address 01h)
register or by reset). Fault criteria: notification from Link Partner of Remote
Fault via Auto-Negotiation.
0 = No remote fault condition detected.
43
Description
www.national.com