CS8420-CS Cirrus Logic Inc, CS8420-CS Datasheet - Page 69

• Manufacturer Part Number: CS8420-CS
• Description: Transceiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8420-CS

• Audio Control Type: Sample Rate Converter
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -10°C To +70°C
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Msl: MSL 2 - 1 Year
• Frequency Max: 108GHz
• Bandwidth: 20kHz
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TCBL - Transmit Channel Status Block Start
TCBLD - Transmit Channel Status Block Direction Input
EMPH - Pre-emphasis Indicator Input
COPY/C - COPY Channel Status bit Input or C bit Input
ORIG - ORIG Channel Status bit Input
AUDIO - Audio Channel Status bit Input
V - Validity bit Input
U - User Data bit Input
CEN - C bit Input Enable Mode Input
DS245PP2
When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block,
and low at all other times. When operated as input, driving TCBL high for at least three OMCK clocks
will cause the current transmitted sub-frame to be the start of a channel status block.
Connect TCBLD to VD+ to set TCBL as an output. Connect TCBLD to DGND to set TCBL as an input.
In mode 6B, EMPH pin low sets the 3 EMPH channel status bits to indicate 50/15 s pre-emphasis. If
EMPH is high the 3 EMPH channel status bits are set to 000 indicating no pre-emphasis.
In mode 6B, the COPY/C pin determines the state of the COPY, PRO and L Channel Status bits in the
outgoing AES3 type data stream (See Table 13). In mode 6A, the COPY/C pin becomes the direct C bit
input data pin.
In mode 6B, the ORIG pin determines the state of the COPY, PRO and L Channel Status bits in the
outgoing AES3 type data stream. See Table 13.
In mode 6B, the AUDIO pin determines the state of the audio/non audio Channel Status bit in the
outgoing AES3 type data stream.
In modes 6A and 6B, the V pin input determines the state of the validity bit in the outgoing AES3
transmitted data. This pin is sampled on both edges of the ILRCK.
In modes 6A and 6B, the U pin input determines the state of the user data bit in the outgoing AES3
transmitted data. This pin is sampled on both edges of the ILRCK.
The CEN pin determines how the channel status data bits are input. When CEN is low, hardware mode
6A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected channel
status data. When CEN is high, hardware mode 6B is selected, where the COPY/C pin is used to enter
serial channel status data.
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