CS8420-CS Cirrus Logic Inc, CS8420-CS Datasheet - Page 33

• Manufacturer Part Number: CS8420-CS
• Description: Transceiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8420-CS

• Audio Control Type: Sample Rate Converter
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -10°C To +70°C
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Msl: MSL 2 - 1 Year
• Frequency Max: 108GHz
• Bandwidth: 20kHz
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

11.5
RUN
CLK1-0
OUTC
INC
RXD1-0
DS245PP2
7
0
Clock Source Control (4)
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control
register, various Receiver/Transmitter/Transceiver modes may be selected.
RUN
0 - Internal clocks are stopped. Internal state machines are reset. The fully static
1 - Normal part operation. This bit must be written to the 1 state to allow the CS8420
these bits are changed during normal operation, then always stop the CS8420 first (RUN = 0),
then write the new value, then start the CS8420 (RUN = 1).
00 - OMCK frequency is 256*Fso(default)
01 - OMCK frequency is 384*Fso
10 - OMCK frequency is 512*Fso
11 - reserved
0 - OMCK input pin (modified by the selected divide ratio bits CLK1 & CLK0,
1 - Recovered Input Clock
0 - Recovered Input Clock (default)
1 - OMCK input pin (modified by the selected divide ratio bits CLK1 & CLK0)
00 - 256*Fsi, where Fsi is derived from the ILRCK pin (only possible when the
01 - 256*Fsi, where Fsi is derived from the AES3 input frame rate
10 - Bypass the PLL and apply an external 256*Fsi clock via the RMCK pin. The AES3
11 - Reserved
The RUN bit controls the internal clocks, allowing the CS8420 to be placed in a
Output side master clock input (OMCK) frequency to output sample rate (Fso) ratio selector. If
Output Time Base
Input Time Base Clock Source
Recovered Input Clock Source
“powered down”, low current consumption, state.
6
control port is operational, allowing registers to be read or changed. Reading and
writing the U and C data buffers is not possible. Power consumption is low (default).
to begin operation. All input clocks should be stable in frequency and phase when
RUN is set to 1.
default)
serial audio input port is in slave mode, default)
receiver is held in synchronous reset. This setting is useful to prevent UNLOCK
interrupts when using an external RMCK and inputting data via the serial audio
input port.
CLK1
5
CLK0
4
OUTC
3
INC
2
RXD1
1
CS8420
RXD0
0
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