CS8420-CS Cirrus Logic Inc, CS8420-CS Datasheet - Page 63

• Manufacturer Part Number: CS8420-CS
• Description: Transceiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8420-CS

• Audio Control Type: Sample Rate Converter
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -10°C To +70°C
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Msl: MSL 2 - 1 Year
• Frequency Max: 108GHz
• Bandwidth: 20kHz
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AES3/SPDIF Transmitter Interface:
TXN, TXP - Differential Line Driver Outputs
TCBL - Transmit Channel Status Block Start
AES3/SPDIF Receiver Interface:
RXP, RXN - Differential Line Receiver Inputs
RMCK - Input Section Recovered Master Clock Output
RERR - Receiver Error Indicator Output
EMPH/U - Pre-emphasis Indicator Output or U-bit Data Input
COPY - Copy Channel Status bit Output
ORIG - Original Channel Status Output
PRO/C - Professional Channel Status bit Output or C-bit Data Input
AUDIO/V - Audio Channel Status bit Output or V-bit Data Input
DS245PP2
Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420
is in the reset state.
When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block,
and low at all other times. When operated as input, driving TCBL high for at least three RMCK clocks
will cause the current transmitted sub-frame to be the start of a channel status block.
Differential line receiver inputs, carrying AES3 type data.
Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi).
This is also a start-up option pin, and requires a pull-up or pull-down resistor.
When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is
updated once per sub-frame of incoming AES3 data. Conditions that cause RERR to go high are: parity
error, and bi-phase coding error, as well as loss of lock in the PLL. This is also a start-up option pin,
and requires a pull-up or pull-down resistor.
The EMPH/U pin either reflects the state of the EMPH channel status bit in the incoming AES3 type
data stream, or is the serial U-bit input for the AES3 type transmitted data, clocked by OLRCK. If
indicating emphasis EMPH/U is high when the incoming data indicates 50/15 s pre-emphasis and low
otherwise.
The COPY pin reflects the state of the COPY Channel Status bit in the incoming AES3 type data
stream. This is also a start-up option pin, and requires a pull-up or pull-down resistor.
SCMS generation indicator. This is decoded from the incoming category code and the L bit. A low
output indicates that the audio data stream is 1st generation or higher. A high indicates that the audio
data stream is original. This is also a start-up option pin, and requires a pull-up or pull-down resistor.
The PRO/C pin either reflects the state of the Professional/Consumer Channel Status bit in the incoming
AES3 type data stream, or is the serial C-bit input for the AES3 type transmitted data, clocked by
OLRCK.
The AUDIO/V pin either reflects the state of the audio/non audio Channel Status bit in the incoming
AES3 type data stream, or is the V-bit data input for the AES3 type transmitted data stream, clocked by
OLRCK.
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