NCP5393MNR2G ON Semiconductor, NCP5393MNR2G Datasheet - Page 19

• Manufacturer Part Number: NCP5393MNR2G
• Description: IC CTLR 2/3/4PHASE CPU 48-QFN
• Manufacturer: ON Semiconductor

Specifications of NCP5393MNR2G

• Applications: Multiphase Controller
• Current - Supply: 25mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5. Fault Responses
CONDITION
VDD Global
OCP
NB OCP
VDD
Per-Phase
Current Limit
Output OVP
-
Infrequent
Output OVP
-
Frequent
Output UV
Monitor
Unused
Phase of
VDD
Regulator
VDDNB
Disabled
5 V UVLO
12 V UVLO
DRVON is
Pulled Low
by External
Means
NB_DRVON
is Pulled
Low by
External
Means
ENABLE is
Low
All to High-Z
All to High-Z
phase set to
Latched Low
All to High-Z
All to High-Z
All to High-Z
Held Low for
OUTPUT(s)
Low or Mid
(See Notes
(See Notes
duration of
Unaffected
Unaffected
Unaffected
Affected
High-Z
High-Z
Set to
Set to
PWM
state
³ )
³ )
OV
Latched Low
Latched Low
Held Low for
Latched Low
Held Low for
by NB status
PWRGOOD
Unaffected
duration of
duration of
Unaffected
Unaffected
Held Low
Held Low
Held Low
Held Low
Held Low
OV plus
500 ms
UV
weak pull-up
Low until 5 V
and 12 V are
Low until 5 V
and 12 V are
Latched Low
Latched Low
While Low a
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Held Low
turns on
DRVON
(VDD)
OK
OK
http://onsemi.com
NCP5393
19
DRVON (NB)
weak pull-up
Low until 5 V
and 12 V are
Low until 5 V
and 12 V are
Latched Low
Latched Low
Latched Low
While Low a
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Held Low
turns on
OK
OK
cause, and let
cause, and let
ENABLE High
VCC (5 V) or
above UVLO
above UVLO
NB_DRVON
Raise +12 V
or +5 V and
or +5 V and
Raise +5 V
DRVON go
underlying
underlying
METHOD
12 VMON
Threshold
Threshold
ENABLE,
ENABLE
ENABLE
Address
Address
RESET
go High
Assert
+12 V
+12 V
Cycle
Cycle
Cycle
High
May eventually cause a
Global OCP or Output UV.
“Infrequent” = fewer than 17
events per 4096/Fpwm
seconds (e.g., 4.096 ms at
Core PWM = 1 MHz)
“Frequent” = 17 or more
events per 4096/Fpwm
seconds (e.g., 4.096 ms at
Core PWM = 1 MHz)
5 V and 12 V UVLO are the
only modes which will force
re-evaluating the phase
count.
5 V and 12 V UVLO are the
only modes which will force
re-evaluating the phase
count.
VDD will try to regulate to
0 V. DRVON low will cause
VDD MOSFETs to turn off.
Both VDD & VDDNB will go
through a SS upon recovery.
VDDNB will try to regulate to
0 V. With NB_DRVON Low,
all VDDNB MOSFETs to
turnoff. Both VDD & VDDNB
will go through a SS upon
recovery.
Cycling ENABLE does not
cause the NCP5393 to
re-evaluate the
programmed number of
phases
NOTES