NCP5393MNR2G ON Semiconductor, NCP5393MNR2G Datasheet - Page 15

• Manufacturer Part Number: NCP5393MNR2G
• Description: IC CTLR 2/3/4PHASE CPU 48-QFN
• Manufacturer: ON Semiconductor

Specifications of NCP5393MNR2G

• Applications: Multiphase Controller
• Current - Supply: 25mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SVI - Serial Interface
single master (CPU) to one NCP5393. The master initiates
and terminates SVI transactions and drives the clock, SVC,
and the data SVD, during a transaction. The slave receives
the SVI transactions and acts accordingly. SVI wire protocol
is based on fast-mode I2C.
considered at start-up. The SVI mode operation is explained
in Figure 10. The VID codes from the decoded SVI value are
given in Table 3.
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Table 2. SIX-BIT PARALLEL VID CODES in PVI Modes
SVI is a two wire, Clock and Data, bus that connects a
PWROK is properitery of the SVI protocol and is
Sequencing of events for SVI:
Boot VID is captured from SVC and SVD pins on
rising edge of ENABLE. This capture is
INDEPENDENT of any other signal.
SVI is determined by sampling VID[1] during rising
edge of ENABLE (SVI: VID[1]=0)
SVID[5:0]
00_0000
00_0001
00_0010
00_0011
00_0100
00_0101
00_0110
00_1000
00_1001
00_1010
00_1011
00_1100
00_1101
10_0111
00_1110
00_1111
V
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
1.3500
1.3250
1.3000
1.2750
1.2500
1.2250
1.2000
1.1750
OUT
(V)
SVID[5:0]
01_0000
01_0001
01_0010
01_0100
01_0101
01_1000
01_1001
01_1010
01_0011
01_0110
01_0111
01_1011
01_1100
10_1101
01_1110
01_1111
http://onsemi.com
V
1.1500
1.1250
1.1000
1.0750
1.0500
1.0250
1.0000
0.9750
0.9500
0.9250
0.9000
0.8750
0.8500
0.8250
0.8000
0.7750
OUT
NCP5393
(V)
15
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SVID[5:0]
10_0000
10_0001
10_0010
10_0011
10_0100
10_0101
10_0110
10_1000
10_1001
10_1010
10_1011
10_1100
10_1101
10_0111
10_1110
10_1111
Once SVI is determined, the VID controller is enabled
and increments to the Boot VID at the Soft Start rate
Once the VID controller is enabled, the VID controller
can receive SVI VIDs, but ONLY after PWROK
asserts
If PWROK goes high and an SVI VID is sent prior to
the VID controller reaching the Boot VID, the VID
controller will move to the SVI VID
If a new SVI code is detected during the transition, the
device updates the Target-VID level and performs the
on-the-fly Transition up to the new code.
If PWROK de-asserts, the VID controller reloads the
Boot VID and will move from its current VID to the
Boot VID
SVI is disabled and SVI transactions cannot take place
again until PWROK asserts
V
0.7625
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6325
0.6250
0.6125
0.6000
0.5875
0.5750
OUT
(V)
SVID[5:0]
11_0000
11_0001
11_0010
11_0100
11_0101
11_1000
11_1001
11_1010
11_0011
11_0110
11_0111
11_1011
11_1100
11_1101
11_1110
11_1111
V
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
0.3750
OUT
(V)