ML610Q432A-NNNTC03A7 Rohm Semiconductor, ML610Q432A-NNNTC03A7 Datasheet - Page 89

• Manufacturer Part Number: ML610Q432A-NNNTC03A7
• Description: MCU 8BIT 64K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q432A-NNNTC03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.2.2
• OSCM1, OSCM0 (bits 3, 2)
• OUTC1, OUTC0 (bits 5, 4)
Address: 0F002H
Access: R/W
Access size: 8/16 bits
Initial value: 33H
FCON0 is a special function register (SFR) to control the high-speed clock generation circuit and to select system
clock.
[Description of Bits]
− When switching the high-speed oscillation mode, please first switch back to low speed clock before switching to
Initial value
•
The SYSC1 and SYSC0 bits are used to select the frequency of the high-speed clock (HSCLK) used for system
clock and periphera1 circuits (including high-speed time base counter). OSCLK, 1/2OSCLK, 1/4OSCLK, or
1/8OSCLK can be selected. The maximum operating frequency guaranteed for the system clock (SYSCLK) of this
LSI is 4.2 MHz.
At system reset, 1/8OSCLK is selected.
The OSCM1 and OSCM0 bits are used to select the mode of the high-speed clock generation circuit. RC
oscillation mode, crystal/ceramic oscillation mode, PLL oscillation mode, or external clock input mode can be
selected.
The setting of OSCM1 and OSCM0 can be changed only when high-speed oscillation is being stopped (ENOSC bit
of FCON1 is “0”). At system reset, RC oscillation mode is selected.
The OUTC1 and OUTC0 bits are used to select the frequency of the high-speed output clock which is output when
the secondary function of the port is used.
OSCLK, 1/2OSCLK, 1/4OSCLK, or 1/8OSCLK can be selected.
At system reset, 1/8OSCLK is selected.
other high-speed clock (set the ENOSC bit and SYSCLK bit of FCON1 to “0”).
FCON0
R/W
OSCM1
OUTC1
SYSC1, SYSC0 (bits 1, 0)
SYSC1
0
0
1
1
0
0
1
1
0
0
1
1
Frequency Control Register 0 (FCON0)
R/W
⎯
7
0
OSCM0
OUTC0
SYSC0
0
1
0
1
0
1
0
1
0
1
0
1
R/W
⎯
0
6
RC oscillation mode (initial value)
Crystal/ceramic oscillation mode
Built-in PLL oscillation mode
External clock input mode
OSCLK
1/2OSCLK
1/4OSCLK
1/8OSCLK (initial value)
OSCLK (1/2OSCLK in built-in PLL oscillation mode)
1/2OSCLK
1/4OSCLK
1/8OSCLK (initial value)
OUTC1
R/W
5
1
OUTC0
R/W
4
1
6 – 3
Description
Description
Description
OSCM1
R/W
3
0
ML610Q431/ML610Q432 User’s Manual
OSCM0
Chapter 6 Clock Generation Circuit
R/W
2
0
SYSC1
R/W
1
1
SYSC0
R/W
0
1