ML610Q432A-NNNTC03A7 Rohm Semiconductor, ML610Q432A-NNNTC03A7 Datasheet - Page 351

• Manufacturer Part Number: ML610Q432A-NNNTC03A7
• Description: MCU 8BIT 64K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q432A-NNNTC03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

26.3.5
For differential amplification input, operate SA-ADC in the following procedure.
1. Before starting SA-ADC, start oscillation of the high-speed clock (HSCLK) and wait until the oscillator settles.
2. When HSCLK is within the range from 375KHz to 625kHz, set bit 1 (SACK) of the SA-ADC control register
3. Set differential amplification input by setting bits 1 and 0 (AMPEN1 and AMPEN0) of amplifier control register 0
4. Set amplifier offset register (AMPOFFS) and amplifier gain register (AMPGAIN).
5. When bit 0 (SARUN) of SA-ADC control register 1 (SADCON1) is set to “1” after the amplifier control register
6. A/D conversion results are stored in the SA-ADC result registers (SADR0L, SADR0H), and when A/D conversion
7. A/D conversion is stopped when the A/D conversion terminates, and bit 0 (SARUN) of SA-ADC control register 1
Even if a channel is switched during A/D conversion, the channel that is selected at the start of A/D conversion is
maintained until an A/D conversion termination interrupt occurs.
Figure 26-5 shows the SA-ADC operation timing when channel 0 and channel 1 are selected.
* Amplifier settling time
The power-up time of the amplifier is 30 μs, the settling time of the amplifier after powered up is 64 μs, and the total
time is 94 μs.
Power-up of the amplifier means that amplifier control registers AMPEN1 and AMPEN0 are set from “0” and “0” to
“1” and “1”, respectively.
Notes:
Since the supply current is increased while the amplifier is powered up, set amplifier control registers AMPEN1 and
AMPEN0 to “0” and “0” respectively to stop operating the amplifier if the amplifier is not used.
The A/D conversion time in 500 kHz RC oscillation mode is 46 μs.
(SADCON0) to “0” and when HSCLK is within the range from 1.5MHz to 4.2MHz, set it to “1”. Set bit 0 (SALP) to
“0”.
(AMPCON0) to “1” and “1” and set bits 1 and 0 (SACH1 and SACH0) of SA-ADC mode register 0 (SADMOD0) to
“0” and “1”.
(AMPCON0 ) has been set and then the amplifier has been settled *, the SA-ADC circuit becomes active and staers
A/D conversion.
terminates, the SA-ADC conversion termination interrupt is generated.
(SADCON1) is set to “0”.
A/D operation signal
Operation of the Successive Approximation A/D Converter in Differential Amplification Input
A/D conversion
Figure 26-5 SA-ADC Operation Timing at Differential Amplification Input
AMPEN0
SADINT
SARUN
HSCLK
Amplifier settling time
94μs@Max
Chapter 26 Successive Approximation Type A/D Converter
26 – 18
ML610Q431/ML610Q432 User’s Manual
26.86μs@4.096MHz
Conversion time