ML610Q432A-NNNTC03A7 Rohm Semiconductor, ML610Q432A-NNNTC03A7 Datasheet - Page 349

• Manufacturer Part Number: ML610Q432A-NNNTC03A7
• Description: MCU 8BIT 64K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q432A-NNNTC03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

26.3.3
For direct input, operate SA-ADC in the following procedure.
1. Before starting SA-ADC, start oscillation of the high-speed clock (HSCLK) and wait until the oscillator settles.
2. When HSCLK is within the range from 375KHz to 625kHz, set bit 1 (SACK) of the SA-ADC control register
3. Set the amplifier control register (AMPCON0) and SA-ADC mode register 0 (SADMOD0).
4. When bit 0 (SARUN) of SA-ADC control register 1 (SADCON1) is set to “1”, the SA-ADC circuit becomes active
5. A/D conversion results are stored in the applicable SA-ADC result registers (SADRnL, SADRnH) and when A/D
6. Finally, using bit 0 (SALP) of the SADCON0 register, it is possible to select whether A/D conversion is terminated
Even if a channel is switched during A/D conversion, the channel that is selected at the start of A/D conversion is
maintained until an A/D conversion termination interrupt occurs.
Figure 26-3 shows the SA-ADC operation timing when channel 0 and channel 1 are selected.
Note:
A/D conversion time in 500kHzRC oscillation mode is 46 μs.
(SADCON0) to “0” and when HSCLK is within the range from 1.5MHz to 4.2MHz, set it to “1”.
and performs A/D conversion from the lower channel number that is selected in the SA-ADC mode register
(SADMOD0).
conversion of the largest channel number that is selected terminates, an SA-ADC conversion termination interrupt
(ADSINT) is generated.
(SARUN bit is “0”) or A/D conversion is automatically restarted at termination of A/D conversion of the last
channel.
A/D operation signal
Operation of the Successive Approximation A/D Converter in Direct Input
A/D conversion
A/D conversion
on channel 0
on channel 1
SADINT
SARUN
HSCLK
Figure 26-3 SA-ADC Operation Timing at Direct Input
26.86 μs@4.096MHz
Conversion time
Chapter 26 Successive Approximation Type A/D Converter
26 – 16
ML610Q431/ML610Q432 User’s Manual
26.86 μs@4.096MHz
Conversion time