ML610Q432A-NNNTC03A7 Rohm Semiconductor, ML610Q432A-NNNTC03A7 Datasheet - Page 370

• Manufacturer Part Number: ML610Q432A-NNNTC03A7
• Description: MCU 8BIT 64K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q432A-NNNTC03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

27.2.8
• b2-b0 (bits 2-0)
Address: 0F600H to 0F7FFH
Access: R/W
Access size: 8 bits
Initial value: Undefined
DSmCnB (m= 0 to 63, n = 0 to 7) are special function registers (SFRs) to store segment allocation data.
Each valid bit of DSmCnB becomes undefined at system reset.
When the programmable display allocation function is not used (DASN bit of DSPMOD1 reigster is reset to “0”),
DSmCnB can be used as data memory space (512-byte RAM).
Table 27-3 shows a list of display allocation register B.
[Description of Bits]
Initial value
DSmCnB
The b2 to b0 bits of DSmCnB (m= 0 to 63, n = 0 to 7) are used to set the bits of the display registers (DSPR00 to FE)
that are output to common n of segment m.
Set DSmCnB when the DASN bit of the display control register 0 (DSPCON0) is “0”.
When the DASN bit is “1”, access from the CPU is invalid.
R/W
b2
0
0
0
0
1
1
1
1
Display Allocation Register B (DS0C0B to DS63C7B)
R/W
b1
b7
0
0
1
1
0
0
1
1
7
x
b0
R/W
0
1
0
1
0
1
0
1
b6
6
x
Selects bit 0
Selects bit 1
Selects bit 2
Selects bit 3
Selects bit 4
Selects bit 5
Selects bit 6
Selects bit 7
R/W
b5
5
x
R/W
b4
4
x
27 – 18
Description
R/W
b3
3
x
ML610Q431/ML610Q432 User’s Manual
R/W
b2
2
x
R/W
Chapter 27 LCD Drivers
b1
1
x
R/W
b0
0
x