ML610Q432A-NNNTC03A7 Rohm Semiconductor, ML610Q432A-NNNTC03A7 Datasheet - Page 354

• Manufacturer Part Number: ML610Q432A-NNNTC03A7
• Description: MCU 8BIT 64K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q432A-NNNTC03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

A) When not using Programmable display allocation function (DASN bit of DSPMOD1 register is “0”)
B) When using Programmable display allocation function (DASN bit of DSPMOD1 register is “１”)
DSPRFE
DSPRFD
DSPR02
DSPR01
DSPR00
DSPR04
Unused
Suitable for the dot matrix type LCD panel whose common/segment array is approximated to the bit array of the
display register. One of three types for the display register segment mapping can be selected, the numbe of used COM
pins determines the recommended type. See section 27.2.5, 27.2.9, and 27.3.2 for more detail.
When the programmable display function is not used, display allocation register A and display allocation register B
(See section 27.2.7 and 27.2.8) can be used as 1K-byte data memory.
DSPRFE
DSPRFD
The programmable display allocation function is suitable for the LCD panel of segment type or character type whose
common/segment array is restricted by the design or wiring. Segment mapping of the display register can be assigned
in bit units by programming according to the contents of display allocation registers A and B. Therefore, the display
register array can be changed in flexible and simplify the software process for display. Contents of the registers
A(DSmCnA) specify addresses of the display registers (DSPR00 to FE) and contents of the registers B(DSmCnB)
specify bits of the display registers, that are output to common “n” of segment “m”.
Unused
DSPR4
DSPR2
DSPR1
DSPR0
Figure 27-2 An example of correlation between display register and dot matrix type LCD
Figure 27-3 An example of correlation between display registers and segment type LCD
b
7
4H 4G 4F 4E 4D 4C 4B 4A
2H 2G 2F 2E 2D 2C 2B 2A
1H 1G 1F 1E 1D 1C 1B 1A
0H 0G 0F 0E 0D 0C 0B 0A
t
i
b
7
t
i
6
b
i
t
registers
b
6
i
t
registers
Display
Display
b
5
t
i
b
5
t
i
b
4
t
i
b
4
i
t
b
3
i
t
b
3
i
t
b
2
t
i
b
2
t
i
b
1
i
t
b
1
t
i
b
0
i
t
b
0
i
t
Fixed display
allocation (Type
1)
Programmable
display
allocation
DSPR4
DSPR0
DSPR0
DSPR0
DSPR
…
…
SEG63
SEG3
SEG1
SEG0
bit
…
…
6
2
1
0
SEG63
SEG4
SEG3
SEG1
SEG0
Symbol
27 – 2
23
O
M
4G
C
0C
0B
0A
…
…
4E
22
C
O
M
4F
4D
C
O
M
7
4G
COM
4A
Dot Matrix LCD
…
…
7
0
0
1
4H
4C
O
M
C
6
4B
2E
ML610Q431/ML610Q432 User’s Manual
SEG
2F
16
M
C
O
…
1
..
3
4
4
15
C
O
M
2D
O
M
C
5
2G
2A
2H
2C
2B
1E
M
C
O
4
1F
Chapter 27 LCD Drivers
1D
1G
1A
C
O
M
8
C
O
M
3
M
C
O
7
1H
1C
1B
0E
0F
C
O
M
2
0D
0G
0A
C
O
M
1
C
O
M
2
0H
0C
C
O
M
1
0B
C
O
M
0
O
M
C
0